It's time for us to start Tokyo Electron IR Day. Thank you very much for joining us today despite your busy schedule. I am Yatsuda of IR Department, acting as a moderator in today's session. It is the second time that Tokyo Electron holds IR Day. Last time, we organized IR Day to present our revised midterm environmental goals, newly released products, and our hub of digital transformation, which moved to a new location. We hold IR Day as we find it as a good timing after publishing our first integrated report in August this year. We will present various activities related to ESG, value chain, and corporate value creation. We would appreciate it if you could kindly understand that we cannot talk anything about the current financial performance in this IR Day since it is before the second quarter financial announcement. Let me introduce the eight attendees on our site. Mr. Tetsuo Tsuneishi, Corporate Director, Chairman of the Board. I am Tsuneishi. Thank you very much for joining us today. We're very happy to see so many people joining in this IR Day. We're going to have a three-hour session, very long session. Really appreciate this opportunity. We'd like to share our idea and our basic strategy, including ESG, with focus on ESG. We'd like to talk what we value and how we promote and contribute our growth and the contribution to the society. Also, we'd like to talk about the semiconductor technology innovation in the future and our product strategy. There are so much items we want to share, taking this opportunity. I hope today's meeting will be fruitful for all the people who join us today. Next, Mr. Toshiki Kawai, Representative Director, President and CEO. I am Kawai. Thank you very much for participating in this session despite your very busy schedule. Next, Mr. Yoshikazu Nunokawa, Corporate Director, Executive Vice President, General Manager, Global Business Platform Division, Finance Unit. I am Nunokawa. Thank you very much. Next, Mr. Keiichi Akiyama, Vice President and General Manager, CTSPS Business Unit. I am Akiyama. Thank you very much. Today, I try to talk about leading EUV technology, relevant technologies later. Next, Mr. Isamu Wakui, Vice President and General Manager, ES Business Unit. Next, Mr. Hiroshi Ishida, Vice President and General Manager, TFF Business Unit. I am Ishida. Today, I'd like to present the film deposition new approach on behalf of TFF BU. Next, Ms. Mie Segawa, Vice Division General Manager, Corporate Innovation Division. I am Segawa. Thank you very much for joining us today. Dr. Akihisa Sekiguchi, Deputy General Manager, Corporate Innovation Division. I am Sekiguchi. Later, I'd like to talk about the technology trends and business opportunity for our company. Before starting the presentation, let me explain the flow of today's meeting. The agenda today's meeting is shown on this slide. We will have a two-hour presentation session, including 10-minute break in the middle. After all presentations, we'll have question and answer session. We plan to close this meeting at 5:30 p.m. Japan time. This meeting uses two channels on Webex, providing simultaneous interpretation between Japanese and English. As we explained in our email, you are kindly requested to use apps on PCs or mobile terminals if you plan to ask questions. If you are not going to ask question, you can use telephones. Since this is a meeting for institutional investors and analysts, we appreciate your understanding that we receive questions only from institutional investors and analysts as usual. We'll upload the audio contents of this meeting, both in Japanese and English later. We will be happy if you also refer to them. Now, Mr. Kawai, CEO, will present "Aiming for Global Excellent Company," talking about our major initiatives for value creation and value chain. Good afternoon. I am Kawai of Tokyo Electron. Thank you very much for joining us in our IR Day today despite your busy schedule. Like last year, due to the COVID-19 spread, we hold this IR Day as an online meeting. I'm very delighted to talk with you in this opportunity. Along with the shift to data-driven society and to decarbonization society, the semiconductor device is becoming increasingly important. Accordingly, our company is expected to exercise more and more important roles and responsibilities. The title of my presentation today is "Aiming for Global Excellent Company." I'd like to present the business environment and our major initiatives. When I look back the situation of the world from last year to this year, we have been struggling with the global spread of the COVID-19 infection and a number of natural disasters in climate, such as torrential rains in Japan, hurricanes and cold waves in North America, and wildfires. There have been various issues globally, including geopolitical issues like trade frictions and human rights issues, which have had considerable impacts on our society and our daily life. In parallel, digital transformation proceeded in our life and every industry last year, which highlighted the significance of the semiconductor devices essential for ICT. The transition to the data-driven society is progressing at an unprecedented speed. Also, we need to address the global environmental problems. Amid those circumstances, the tidal wave of digital and green is spreading across the world. What I mean by green here is carbon neutral, aiming at decarbonization to suppress CO2 emissions. In order to build a strong and resilient society in which economic activities are not disrupted in any situations, the world is implementing ICT and digital transformation and striving to realize a decarbonized society. In the future, digitalization in every industry, such as autonomous driving, smart city, smart factory, smart agriculture, and smart medicine, is expected to spread widely through the society. It is semiconductor devices that support all of these at their bedrock. The semiconductor devices used to be dubbed as rice of the industry in Japan, meaning the essential building block of the industry. Now, as an essential building block of the industry, society, and our life, it is playing wide-ranging roles. In the past, the semiconductor market was driven by products, mainly by electronic devices such as PC and smartphone. At present, various services using data, in other words, value, that people want to realize are the main drivers. It is about 70 years since the transistor was invented in 1947. The global semiconductor market was about $440 billion in 2020. The market size is expected to reach about $1 trillion in 2030. This means the market will be more than doubled in size in the next decades. In 10 years' time, we will see another market of the equal to the current market in size. Accordingly, WFE market size is expected to exceed $90 billion in 2021, but it is just the beginning. Electric vehicle, fuel cell vehicle, and autonomous driving will be spreading. In addition, 5G will be widely adopted. In parallel, post-5G development will be proceeding. To realize ICT, digital transformation, and decarbonization, the semiconductor is required to have more storage, faster speed, and higher reliability with lower power consumption. Accordingly, the WFE market will grow furthermore. This slide shows the trend of WFE market that our company analyzes. The blue on the left represents the past, while the green on the right represents the future. As you know, in the past, semiconductor market growth was driven by emergence of new models of PC and mobile phones. Therefore, once their supply got stabilized, the demand for semiconductor devices slowed down, which was called silicon cycle. The arrival of data-driven society together with IoT, however, triggers an explosive increase of the semiconductor demand. Continuous capital investment to leading-edge semiconductor devices, supporting value-driven consumption is essential. The IC manufacturers having high market share are strongly aware of supply-demand balance. Based on these factors, we believe the WFE market has entered a new phase in which it will grow strongly in a staircase shape. As I said so far, due to high expectation to the semiconductor and WFE market, Tokyo Electron is expected to exercise more and more roles and responsibilities toward the future. As our corporate purpose, Tokyo Electron implements our corporate philosophy. We strive to contribute to the development of dreams-inspiring society through our leading-edge technologies and reliable service and support. Specifically, the implementation of the corporate philosophy means that by leveraging the expertise of the process to manufacturer, we will make an effective use of all resources, including the employees who are the source of value creation, contribute to both digitalization and greening through the semiconductor technology innovation to expand the longer-term profit, enhance corporate value continuously, and make all people around our company happy. Based on this concept, we published our integrated report in August this year. Today, I will touch upon our efforts for value creation. That is one of the topics presented in this integrated report. To expand the longer-term profit and enhance corporate value continuously, we have defined our materiality. Based on the management foundation, including safety, quality, governance, compliance, and risk management, our materiality is composed of product competitiveness, customer responsiveness, and higher productivity. To intensify this materiality, we will implement the strategy, making the maximum use of our expertise and strength. Our strengths are shown here. One and only WFE manufacturer offering process tools for the four consecutive processes essential for the advanced device patterning technologies. Our share in these products ranks number one or number two in the world. In particular, we maintain 100% share in coater/developer for EUV lithography, which is essential for the leading-edge device nodes. We have the world's largest installed base of about 78,000 units, which increases by 4,000 units every year. Based on this, we have built a Field Solution business model. Based on these strengths, we will keep a productive R&D investment to create innovative technologies leading the world. By aligning technology roadmap of multiple generations with the customers and supporting their manufacturing lines of the current device nodes, we will develop products with high success probability and create unique high-value-added technologies that only TE L can develop to support digital and green. For manufacturing aspect as well, we have been building our infrastructure. In 2020, the new production building started operation in Tohoku Plant and Yamanashi Plant. In May this year, we announced that we acquired the land in Miyagi Plant, where we'll support the stable supply to address rapidly growing semiconductor demand. Toward the sustained growth of our business activities, we are building a resilient supply chain based on the solid relationship of trust with our partner companies. For our partners, we perform STQA, Supplier Total Quality Assessment. Every year, we conduct CSR BCP, and survey on conflict minerals and environmental laws and regulations to promote the supply chain management. We have established Miyagi Technology Innovation Center last month, aiming at merging diversified technologies of our suppliers to create new innovation. We will keep working on sustained growth of the industry through collaboration with the partner companies. Next, I will talk about our sustainability efforts, including the ESG initiatives in our value chain. To contribute the development of international community, we are promoting the sustainability efforts through our business operation. We have linked the United Nations SDGs and our corporate materiality. We carry out groupwide activities and also participate in international initiatives. Along with their framework, we analyze impacts on our opportunity of our business and disclose relevant information. Our activities are highly recognized across the world. We have been selected on the list of global leading ESG investment indices. We will make a continuous effort so that we can win trust from our stakeholders. We are working on reduction of CO2 emissions with the three perspectives. The first perspective is to contribute to enhance per-watt performance and reduce power consumption of semiconductor devices through our semiconductor manufacturing technologies. The second is energy conservation of our products and business activities. Toward the midterm environmental goals of 2030, one of the most demanding goals in the industry, we will strive for decarbonization. For 70% reduction at our sites, we mainly work on 100% renewable energy use. Yamanashi and Miyagi Plant have already switched to renewable energies at 100%. Kumamoto and Iwate plants plan to switch next year. The third is the E-COMPASS initiative that we announced in June this year. This is a new initiative to build sustainable supply chain and promote global environmental conservation activities throughout the supply chain. I will talk about our efforts for safety, in particular incident. This figure shows TCIR, total case incident rate, per 200,000 working hours. The dotted lines represent the average of material vendors, IC vendors, and tool vendors. The solid lines indicate the value of IC vendors A and B, and those of competitors C and D, as well as our own values. As you can see, our company fits in world-class safety. While expanding the business size, we maintain high level of safety. What we aim at, however, is zero incident. Under the banner of safety first, we will make every effort to improve safety in every business activity of our company. It is our employees that perform all of our business activities and realize our sustained growth. It is people that drives the company. Employees are the source of value creation. Based on that idea, we focus on the three things. First of all, code of conducts, which is based on the corporate culture we have committed ever since our foundation. We call it TEL Value to be shared with our employees. The second is motivation-based management. Employees' performance is determined by their ability and motivation. They were screened by ability when they entered the company. Motivation is critical to raise their performance. To enhance their motivation, it's important that they have dreams and expectations for the future of the company. They have an opportunity to challenge without fear based on strong financial basis. They are fairly evaluated and recognized with globally competitive reward, and they can communicate openly. We are taking various measures to enhance the employee engagement, such as introduction of new HR system designed to facilitate dialogue between supervisors and subordinates. The third is diversity and inclusion, focusing on perspective 3G, namely global, generation, and gender. We will announce specific goals this year to reflect them in the corporate governance guideline. This slide shows the code of conduct, TEL Value that I talked about. Pride, challenge, ownership, teamwork, and awareness. You can see the idea of each of the five. In challenge, for example, it states we will be generous for failure and highlight importance to learn from its process and result. This represents our basic idea in TEL. Fiscal year 60 starts in April 2022. Based on TEL Value, we will explore a new era to keep being dream-inspiring and vivid company. At present, we are operating 76 sites in 18 countries throughout the world. Looking at the customer's future investment plan, however, we expect our sites, employees, and suppliers will further increase. We are determined to be highly aware of human rights, including employment conditions, work environment, and occupational health and safety throughout our supply chain, and contribute to development of dream-inspiring society. To increase our longer-term profit and enhance our corporate value, we set the goals of operating margin and ROE in the midterm management plan, which is our offense management strategy. In parallel, we are committed to safety, quality, compliance, employee engagement, risk assessment, and security. These activities, essential for our business sustainability, are defense strategy, and at the same time, it's our strength. Each one of the employees will work on these to further strengthen our management foundation. Affluent future the semiconductor device realize. Ever-evolving semiconductor device. The WFE market supporting semiconductor devices now in the further growth phase. The corporate growth is driven by people. The employees are the source of value creation. Tokyo Electron will implement the corporate philosophy, leverage our expertise and diversified resources, create innovative, high value-added technologies that only TEL can create, and provide these technologies to the society. We will keep challenging and evolving from now on. We aim at true global excellent company, strongly trusted by all the stakeholders. Thank you very much for your kind attention. Next, Ms. Segawa, Vice Division General Manager, will present supply chain initiatives for the environment. I am Segawa, Vice Division General Manager of Corporate Innovation Division. I will present E-COMPASS, our supply chain initiative designed to enhance the environmental conservation efforts. On June 16, 2021, we announced the initiation of E-COMPASS, the supply chain initiative focusing on the environment. E-COMPASS is an abbreviation of environmental co-creation by material process and sub-component solutions. E-COMPASS also represents environment compass. We want to make this initiative a real compass leading our community. The logo shown in this slide expresses our resolution toward this initiative. "C" of E-COMPASS uses a symbol of infinity, expressing sustainable use of resources and energy, and permanent relationship with our stakeholders. The color gradation from blue to green represents our future journey toward environmental footprint reduction through co-creation with our partners. This is one of the important initiatives in pursuing our corporate philosophy to realize digital and green society that Kawai-san said earlier. I will present the three underlying factors of this new initiative foundation. The first one is climate change. As you know, over the past few years, unprecedented massive disaster took place in many parts of the world. Climate change induced by global warming is one of the factors to cause these disasters. The international community is raising awareness of environmental issues, regarding them as intimate crisis for us. As all business across the world are expected to address the environmental issues, the IT industry is no exception. Our customers, namely IC manufacturers, become increasingly aware of the environment. Tokyo Electron, as a global citizen doing business on this planet, is determined to be responsible for building the supply chain with high level of awareness of the impacts on climate change. The second factor is an increasing trend of international treaties and legal requirements for the environment. This figure shows that international treaties, laws, and regulations for the environment have been increasing year by year, which is on the horizontal axis. Some of these legal requirements have significant impact on business activities. In order to prevent the legal requirements from becoming our business risks, we need to assess the future trend and take proactive approach. An effort to minimize business risk in the entire supply chain will become increasingly important. This slide shows the third factor. Now that the semiconductor industry becomes essential in the society, Tokyo Electron must take responsibility as a company aiming at the global excellent company and take leadership in achieving sustainability in the entire industry. We deliver our products to IC manufacturers to help them realize leading-edge devices featuring high performance and low power consumption. As IC devices manufactured by applying our leading-edge manufacturing technologies are widely used in the society, they will contribute to reduction of environmental impacts for years to come. Dr. Sekiguchi will present the details of reduction of environmental impacts through our manufacturing technologies. Our business activities to pursue both digital and green are supported by the alliance with many partners. In order to raise awareness of the environment together with the partners, we launched E-Compass as a supply chain initiative focusing on the environment. This shows mission, vision, and value of E-Compass. The mission is that we will promote green performance enhancement of microelectronic industry through supply chain-wide collaboration to reduce global environmental impacts. The vision is that we will work on the green technologies in the entire supply chain to co-create sustainable and affluent future where humans and nature coexist. The value is that we will provide high green performance microelectronics manufacturing technologies and process tool technologies, address legal regulatory requirements, and reduce environmental footprints in our operations under this mission and vision. By implementing the mission, vision, and value of E-Compass through our business activities, TEL will make use of all resources to realize both digitalization and greening in the society. By promoting our active environmental initiative, we will pursue our corporate philosophy. We strive to contribute to the development of dream-inspiring society through our leading-edge technologies and reliable service and support. Next, let me talk about specific E-Compass activities. There are three major pillars. The first one is to pursue sustainability in the entire industry through enhancement of partnership. The second one is to provide environmentally conscious products by realizing process tools free from environmentally hazardous materials. The third is to accelerate innovation of manufacturing technology by proactively developing green technologies. We will work on these activities to promote environmental impact reduction and green technology innovation in the entire supply chain. Next, I will talk about what we are doing in these three activities. The first activity is enhancement of partnership. This slide shows CO2 emissions in the entire value chain of our company. In comparison with CO2 emissions of TEL itself, which is 186,000 tons, the CO2 emissions in Scope 3, which covers upstream and downstream of supply chain, is more significant. The CO2 emissions in downstream, in particular, attributed mainly to use of our products. Enhancing environmental performance of our product directly leads to the reduction of the environmental impacts of entire semiconductor industry. We will encourage our partners to understand the mission of E-COMPASS, to enhance green performance of microelectronics industry, and strive to establish solid partnership. This shows examples, reduction of environmental impacts in procurement distribution. The example on the left is modal shift between the suppliers in Western Japan and our Kyushu and Miyagi sites. Truck transportation has been replaced by railroad transportation to reduce CO2 emissions. From this fiscal year, modal shift effort will be expanded to the suppliers in Kyushu so that we can further reduce CO2 emissions. The example on the right is introduction of returnable packages and containers, such as plastic trays, and innovation of packaging materials to reduce consumption of air caps and disposable carton boxes. In the upstream of our value chain, each one of these activities may look insignificant, but we will review each business activity and accumulate small improvement, little by little, so that we will raise awareness among ourselves and our partners. The second activity is to develop process tool free from environmentally hazardous substances. Our process tools are composed of parts manufactured by many partners to be delivered to our customers. We believe it is important to build supply chain pursuing minimization of environmental impacts, since the environmental regulations are rapidly increasing. By enhancing the alliance with our partners, we will be able to eliminate substances of environmental concern from the component we purchase and provide environmentally friendly products to our customers, so that customers can use our products for years with peace of mind. We can build a solid relationship of trust, not only with the customers, but also with all stakeholders, and eventually enhance our corporate value. Now, let me show you some specifics. As a first step, we will learn from Europe and the United States, which are advanced in environmental initiative, proactively identify substances of concern for negative impacts on environment and human body, and share the information with the partners. For the substances of very high concern, we will proactively find alternatives and develop a method to minimize their release to the environment. Joint technology innovation with partners may be very useful for us. The third activity, the last one, is to develop the green technologies proactively. The traditional product specifications were composed of hardware and process performance specifications, and operation safety specifications. We will add environmental specifications to accelerate development of green technologies for our best products and best technical services. The green technologies will serve as our competitive edge to facilitate the technology innovation. Use of energy, water, and chemicals require drastic technology innovation. We will enhance the alliance with our partners so that we can propose attractive solutions leading to reduction of environmental impacts. Every site of TEL has accelerated development of green technologies. Let me present an open innovation together with the partners. This is Miyagi Technology Innovation Center, whose construction was completed on September 22nd, 2021. This center was built to enhance development of innovative manufacturing technologies at TEL Miyagi, which manufactures etching systems. The center leads the development to drastically improve performance, quality, and lead time of our products, and it also have lab area and open innovation areas, where we can use for the collaboration development. Making active use of this co-creation area, we will promote development of green technologies in the E-COMPASS initiative. In my presentation, I presented our activities of E-COMPASS initiative. To implement the value of E-COMPASS, that is, we will provide high green performance microelectronics manufacturing technologies and process tool technologies, address legal and regulatory requirements, and reduce the environmental footprints in our operations. We will explore new partners and seize technologies in the world to facilitate the activities. Really appreciate your continuous support. Thank you very much for your kind attention. Next, Dr. Sekiguchi, Deputy General Manager, will present technology trends and TEL's business opportunities. Thank you very much, Yatsuda-san. I'm Sekiguchi, Deputy General Manager of Corporate Innovation Division. I will talk about technology trends and TEL's business opportunities. This is today's agenda. Firstly, I will talk about the recent market trends. I will share my ideas about how these market needs will impact development semiconductor devices, and how logic, memory, CMOS image sensor, and other leading devices will evolve. Finally, I will present the direction of our development activities and future needs. Before getting into the complicated topics, however, let me warm up a little bit. I use these two photographs quite often in conferences recently. On the right, you can see Ford Model T, a car more than one century ago. It was manufactured in an innovative process of low-cost, high-volume production. It features 20 horsepower. Maximum speed was about 70 km per hour. It is quite fast, but in terms of safety, the Model T is far behind the autonomous driving vehicle, which uses numerous sensors to bring its passengers safely without any stress to their destination. The autonomous driving vehicle is a kind of collection of semiconductor technologies. Ford did have one unique feature that even supercar on the left cannot match. That is, it can operate and can be made without any semiconductor devices. What I want to highlight here is not about the restriction due to the tight supply of semiconductor devices, but about the automobiles have grown to become a platform to drive the semiconductor industry, although it took some time so far. Some more information. I am sorry, let me add some more. Semiconductor radio was mounted to Chevrolet model in 1922. At that time, price of the car was $850, while the radio was $200. Electric vehicle was originally invented in 1830. Its share grew gradually until 1870, but it was driven out of the market by cheap Model T. I sense something in common with semiconductor technology in this story, such as technology innovation and cost reduction. At present, semiconductor device is essential for a car, logic, memory, sensor, communication, and display. Various semiconductor devices are mounted on a car. An instantaneous decision made by AI on edge side, which is essential for autonomous driving. Building communication infrastructure to send data collected by sensor through high-speed network is also essential. The cloud computing infrastructure, which efficiently process the data, are evolving by using various innovative accelerators. AI accelerator, quantum accelerator are featured in the media, but they are not free from problems. The server farm shown on the right, which looks a little bit untidy, have many problems. Increasing power consumption, heat dissipation, delay taking place every time data are transferred. There are so much room for improvement. This is why there is no end in the research activities. Now that a car is equipped with leading-edge technology node devices, both logic and memory, the car is driving the semiconductor industry as one of the launching platform of the semiconductor technology. Machine and devices generate huge amount of information. The same applies to mobile devices, which has been driving the industry so far. People full of wearable devices, in a sense, is also a platform for the technology. Health monitoring is a promising category to grow in the future. Hobbies are also important, though they are not essential. Biologging, such as Internet of Animals, may generate more data than people in some areas where people like pet. How do these market needs impact the semiconductor device development? This shows our corporate technology vision. I have shown this before several times. The arrow in the middle represents continuation of Moore's Law. The arrow indicating main device evolution is very healthy. The green arrow indicates customization, while the purple arrows represent HiPerMOS. In other words, the purple represents the needs of productivity enhancement or continuation of legacy nodes. The blue in the middle represents device scaling, 3D device structure, and new material development. The green represents SDTCO, namely system device technology co-optimization and new architecture. The system integration supporting device hybridization is part of this green arrow. I will present more about this system integration. For system integration, there are four different categories. From the left, logic, memory, back-end of line, and other options such as bonding. I will go one- by-one. First, logic. You can see 2D shrink as an extension of device scaling, new structure, and DTCO to co-optimize device design and process technology. This shows memory. Here again, 2D shrink. More stacking for storage enhancement and 3D DRAM to break through the planar device shrink. The third one, this is back-end of line interconnect in process. To reduce data transfer delay, a new technology to embed memory and accelerator on-chip instead of off-chip is in progress. As many of next-generation memories can be embedded to interconnect structure, technologies to embed various memory structures to back-end of line is being developed now. NPU, or neural processing unit, is developed to make device have multiple functions. In addition to the conventional SoC with CPU and GPU embedded, we can also see SoC with NPU dedicated to machine learning embedded. Number four, this shows heterogeneous integration, which is driven by evolution of bonders. I'll talk about it later on in my presentation. We must not forget SDGs, Sustainable Development Goals, initiated by the United Nations. Tokyo Electron is working mainly on seven items. Our contribution is not limited to our own premises or products. This is the information we borrow from imec, a Belgian consortium and our development partner. On the left, the vertical axis shows the normalized environmental KPI, while the horizontal axis shows logic technology node. Energy cost and water consumption in the logic production are plotted here. Leading-edge logic feature the lowest environmental impacts. The environmental impact per device when it is produced by using leading-edge technology is lowest, and our process tools are essential for the production of leading-edge devices. I will talk about this issue later in GAA. Direction of the development of semiconductor devices. You can see important message under each device. The logic, the scaling with its structure change for cost reduction per transistor, lower power, and faster device. NAND, higher stacking to reduce cost per bit. DRAM, scaling and new structure will enable reduction of cost per bit, lower power, and faster device. CIS, CMOS image sensor, increase of pigments by scaling, faster speed, high image quality driven by new structure and materials. Now, let me talk about trend and business opportunities of logic device. On the right, you can see smartphone CPU evolution from 2014 to 2020. Over the past five generations, the number of transistors has been increased six times using the same die size, and the number of cores has been tripled. Now you can see brand-new 16 NPUs as well. Memory cache size has been increased by about six times. Due to evolution of structure, material, and patterning technology, level of integration and function improved drastically. Similarly, GPU performance has dramatically improved at the same time. There was another option to reduce number of transistors to reduce chip area. In the case of HPC, priority was placed on improvement of PPAC performance. Scaling is essential to increase the level of integration. The key enabler is the patterning using EUV lithography and gap fill technology. For the final patterns, etching technologies with high selectivity suitable for various materials and dry technology to prevent pattern collapse. These are very important technologies. What is essential to realize DTCO is various etching technologies with high selectivity and dielectric film and metallic film deposition technologies. This shows the logic roadmap from N7 node to N0.7 from left to right, showing measure device parameters. When PP, poly pitch, times MP, metal pitch, are compared, integration will increase by a factor of 5.7. If DTCO cell height is included, integration per unit volume will be 23 times. To increase integration that much, we need to develop GAA, the Gate-all-around, the new device structure. The GAA is also called nanosheet. The vertical fin channel is placed horizontally to be made in a state of sheet, to increase the number of stacking layers to meet performance specifications. A major characteristic is that fin width, 1 of the critical dimensions determined by patterning in the case of fin device, will be replaced by sheet thickness, determined by silicon epitaxial growth. A large number of our technologies are used for formation of GAA, the core of the device. I'll talk about it later on. The major modules for the GAA formation are shown on the right-hand side, starting with Multistack and Etch. Next, formation of inner spacer, followed by nanosheet release, and after that, we'll see the replacement gate process. This is what we borrowed from IBM Research in New York State, one of our development partners. The cross-section of 2-nanometer gate-all-around technology. You can see very good nanometer profile. This GAA requires advanced process technologies to make. The GAA device fabrication process is divided into four process modules. Number one, from the left to right, the first one is Multistack and Etch. STI, shallow trench isolation, and silicon-germanium stacking layer are epitaxially grown. The second is inner space module. This includes recess processing to control device characteristics and spacer formation. The third is nanosheet release module. Depending on device type, silicon or silicon-germanium layer is removed. This requires high selectivity etching process. The last one is replacement gate module to fabricate gate electrode. Here, film deposition and etching technologies play an important role. Here are actual examples, but because of time limitation, let me just skip this slide. This shows patterning technology using EUV, which is also essential for GAA device. As you know, EUV lithography features high resolution due to its short wavelength. Compared with ArF, however, the number of EUV photons per dose is limited to 1/14. As EUV features lower photon absorption reaction rate than ArF, EUV allows stochastic noise generation, which makes pattern rougher. Our company succeeded to reduce the roughness by co-optimizing conditions of exposure and etching. What we need is global development sites. There are limited source or routes that we can get EUV exposed wafers. By collaborating with European, American consortia and our customers, Tokyo Electron is promoting advanced process technology development. This shows the deliverables of the collaboration. Could you follow the CD SEM images from left to right? Originally, this nanopattern featured critical dimension of 14.7 and line edge roughness of 2.25. The CD was reduced to half and line edge roughness has been also improved, 1.5 nanometer, by using our technologies. In the previous slides, I presented next-generation GAA logic. Next, I'll talk about two generations ahead, stacking of GAA structure. This is CFET structure shown on the right, and bonding technology is a key. Bonders have been widely used for CMOS image sensors. For logic, it's used to fabricate backside PDN. Today, unfortunately, because of the time limitation, I cannot give you any details. If you are interested in, please let us know to our 3DI group. I take so much time for logic. I'd like to talk of memory and CMOS image sensor. As shown here, DRAM is full of high aspect ratio structures. Degree of freedom on the XY axis is very much limited. Pitch scaling is very difficult. Common shrink and scaling are very difficult. There have been evolutions over the past six years. From 2014 to 2020, data rate has been tripled, and capacity has been raised by about five times. Packaging technology with logic has evolved as well. Combining with GPU, DRAM can be dramatically increased the amount of data that GPU can process at a time by using silicon interposer technology. As you can see from this roadmap of DRAM changes milder compared with logic. 3D DRAM development has been getting active recently. It's too early to present the details, but previously, capacitor structure was vertical. The capacitor is placed now horizontally to be stacked. That's how it's changed. As you can see here, we are developing processes required for formation of stacked capacitor, cell, transistor, and wordline and bitline. I'm getting close to the end of my presentation. NAND integration can be enhanced by increasing the number of stacking layers. Device footprint can be reduced by putting logic cell under memory array. Techniques using monolithic and bonding tool have been established. This shows the NAND technology roadmap. From left to right, year by year, the number of layers per stack keeps increasing. The number of tiers also show a mild increase. Materials for wordline are expected to change in the future. Challenges for 3D NAND technology includes etching to cope with increasing number of stacking layers, film deposition, essential for device formation, cleaning without pattern collapse, and bonding technology again here. Finally, I will briefly touch upon the CMOS image sensor. Just like other devices, device hybridization is proceeding for image sensor. The sensor and logic are combined, and AI processing is also added, and you can see increase in applications. This shows challenges and solutions for CIS technology. The first one is hybridization. Hybridization is supported by bonding technology to support hybrid product of logic circuit and CIS. Silicon trench etching for device isolation and film deposition and etching for global shutter are also very important. I'd like to summarize my presentation. The semiconductor manufacturer processing is getting diversified and complex, which raises add value of SPE. This shows an update of WFE investment per monthly wafer size of 100,000 that I presented two years ago. Though there are some cases investment drops from two years ago, this is a result of improvement of the tool performance and productivity. This leads to the development technology in the industry, including customers. This is my summary slide. The market needs are getting more and more complex. In order to address those needs, including the multi-functionality, the device evolution is accelerated. In the multifunction or functionality, of course, some of them can be addressed by existing process. Further technology innovation is essential. As Mie Segawa said earlier, environment, SDGs need to be very important when we develop new technologies. This is what I want to emphasize. When we develop the leading edge devices, actually that has a lot to do with SDGs. That's one of the messages I want to convey today. Our company is implementing the process development on the worldwide basis, and we are working on the global collaboration inside and outside the company. The following three presentations my business unit will give you more detailed examples. Thank you very much for your kind attention. Now it's time for us to start the second half of the presentations. Mr. Akiyama, the General Manager of CTSPS BU will present challenges and solution for advanced EUV resist process technology. I am Keiichi Akiyama, General Manager of CTSPS Business Unit. The title of my presentation today is Challenges and Solution Advanced EUV Resist Process Technology. I'll talk about process technology using leading-edge coater and developer. This slide shows the features of CLEAN TRACK LITHIUS Pro Z EUV, our coater/developer for EUV lithography. In these days, as you know, there have been growing demand from IC manufacturers for finer resist patterning technology. EUV lithography is a solution for this demand, and this Pro Z EUV is essential to implement the EUV lithography. The primary strengths of LITHIUS Pro Z EUV are high reliability, high productivity, and high versatility. As an inline process tool, LITHIUS Pro Z EUV maintains 100% share. We have shipped more than 100 systems so far. High reliability and productivity are realized by 2 factors. The first is LITHIUS Pro Z platform, featuring high speed transportation and processing capability. Over the past nine years, more than 1,600 LITHIUS Pro Z platform, have been shipped for exposure system using various light sources. The second factor is that we have developed and installed EUV specific functions to this system. I will explain the details of high versatility to address next generation EUV lithography in the next two slides. This slide shows the logic technology roadmap and corresponding advanced lithography technologies. As of 2021, the EUV lithography has already been used in high volume manufacturing lines. Scaling of minimum metal pattern pitch is going on. In the 5- nanometer node, about 28- nanometer pitch is used, which requires EUV multi-patterning. Finer resist patterning is essential to realize further device scaling. Metal oxide resist, a new high-resolution resist, is expected to be introduced from the 3- nanometer node. An innovative high NA EUV lithography is to be introduced from the device node, the 1.4- nanometer. Tokyo Electron is promoting R&D of our coater/developer to enhance its versatility to address new EUV lithography technologies, including metal oxide resist and high NA EUV. This figure shows the proportion of layers using chemically amplified resist and metal oxide resist in each device node. For logic device, it is expected that the proportion of metal oxide resist featuring higher resolution will gradually increase along with the device scaling. For the time being, however, we think the proportion of chemically amplified resist remains high. The dry resist system of the competitor only addresses metal-containing resists. By contrast, our coater/developer is designed to address all EUV resist process, including chemically amplified resist, which accounts for the majority of the EUV lithography. high NA lithography is expected to grow in number. We are currently developing relevant technologies. There are still various challenges in establishing the next generation EUV lithography process. The first challenge is trade-off of RLS, namely resolution, line edge roughness, and sensitivity. The second is patterning defects, which become increasingly challenging along with further device scaling. The third is the challenge for high volume manufacturing, the necessary resist film thickness. When resist film thickness is reduced for better lithography performance, thin resist film will be damaged by etching to cause defects. When resist film thickness is increased, however, resist pattern will collapse, and resist remains at the bottom hole after development process. In an attempt to overcome these technological challenges, we are working on total optimization of the patterning technology by combining the measures for the coater/developer technology and etching technology. Today, I would like to present some examples of those engineering efforts. Firstly, I will talk about the measures taken for chemically amplified resist, which has been used for a long time. In particular today, I will present how we address resist pattern collapse and increase process margin through the optimization of patterning processes, including etching. This shows the technology to prevent resist pattern collapse, one example of chemically amplified resist optimization. Along with pattern sites scaling, resist pattern collapse becomes a critical problem in the wet development process. As shown in the upper images, 14- nanometer resist pattern with high aspect ratio collapse after conventional post-development rinsing process. The lower images show the patterns treated with newly developed post-development rinsing process. As you can see, even at 11.8- nanometer patterns, which are much finer than the target 14- nanometer resist pattern, do not collapse. By using the new post-development rinsing process jointly developed with material manufacturer, we have succeeded in preventing the pattern collapse problem and increasing process latitude, process margin suitable for high-volume manufacturing. Next, I will talk about formation of fine holes realized by optimizing lithography and etching process. As I said before, residual resist at the bottom of hole after development process is one of the challenges. If the residue can be removed, the device yield will be enhanced. As a result of etching process optimization, 80- nanometer holes with 36- nanometer pitch are successfully transferred without any defects, such as resist residue or kissing of two neighboring holes. The hole of 36- nanometer pitch will be used in the device node of 1.4 nanometer. Another example is shown in the figure on the right. In the lithography process, 23- nanometer holes are fabricated with pitch of 46- nanometer. This hole size was reduced to 13- nanometer through the optimized etching process. This technology to reduce hole size will be presented by ESBU later. We believe it is our prominent strength to realize this kind of optimization promptly, because we have not only detection technology, but also coater/developer technology connected with the advanced exposure system. Far, I presented several examples of process optimization for chemical amplified resist, which has been used in high volume manufacturing line for years. I will talk about our initiatives for metal oxide resist or MOR. Today, I will present improvement of EUV exposure sensitivity, roughness reduction, countermeasures for defects, and resist pattern collapse. This slide shows the demonstrated performance of our newly developed post-exposure bake oven. By applying optimum baking conditions, exposure sensitivity has been improved by about 25% without negative impacts on resist patterns. The exposure sensitivity enhancement will lead to higher throughput of EUV lithography system. Drastic COO reduction is expected. The new oven will also improve the within-wafer CD uniformity of resist patterns to 0.2 nanometer. For the metal contamination in the baking module, which is a specific concern of metal-containing resist, the new oven meets the target for high volume manufacturing line. The new oven is suitable for the MOR, metal oxide resist baking process. This shows the newly developed wet development technology. The conventional wet development process causes the resist pattern collapse problem when it is used for finer pillar patterns with 36- nanometer pitch for the future nodes of DRAM devices. The newly developed wet development technology is able to suppress the resist pattern collapse. This technology also improves exposure sensitivity by 25% without deteriorating uniformity of resist pattern sites. This technology is expected to considerably reduce our customers' cost of ownership of EUV lithography by increasing EUV lithography system throughput through improved exposure sensitivity. We are also working on module solution for metal oxide resist incorporating etching technology. By optimizing our etching technology, we have improved uniformity of post-etching pattern widths to 1.8 nanometer or less, which is essential to raise device reliability. For a bridge defects break in interconnects, the defect density has been reduced below the initial target of 0.1 defects per 1 square centimeter. Through this improvement, even in the case of very fine interconnect of 50- nanometer, yield of almost 100% has been achieved. Our coater/developer technology has been highly optimized for metal oxide resist. We are on track in preparing for the introduction to high volume manufacturing line. Now, I'd like to change the topic from technology to cost. Roughly speaking, there are two types of metal-containing resist process being developed for high resolution. One is wet resist process of metal oxide resist that TEL is now developing. The other is dry resist process, in which resist film is developed by film deposition system and then dry development is performed by etching system. The latter is being developed by our competitor. In the dry resist process using CVD film deposition and dry development, it is essential to remove metal contamination from etch and backside of the wafers, which results in more process steps and higher manufacturing costs. By contrast, the wet resist process, which TEL is developing, does not need any additional process to remove metal contamination. It also features shorter turnaround time. Cost of ownership of wet resist process is expected to be about 1/3 of that of dry resist process. In addition to the benefit of cost of ownership and operating cost, the wet resist process is also found advantageous in terms of process performance. For example, it raises sensitivity to reduce EUV exposure time. It's easy for customer to adopt it. The final topic of my presentation is our activities for high-NA EUV to further enhance resolution. In June 2021, TEL announced that we will deliver our inline coater/developer for high NA EUV lithography system, which will be installed in the imec ASML Joint High-NA EUV Research Laboratory in 2023. Leveraging this research environment, we will collaborate with the partners to establish fine patterning technology for high NA EUV lithography ahead of others. We are working on optimization of pattern scaling solution to prepare for the high NA EUV lithography. This shows fine metal oxide resist pattern processed with the conventional EUV lithography system. The fine patterns of a 12- nanometer half pitch are fabricated by combining the wet resist process and our etching technology. It is demonstrated that wet development process realizes 12- nanometer half pitch patterns with line edge roughness and line width roughness of 2 nanometer or less without causing any pattern collapse. This demonstrate that our new systems are promising for further pattern scaling in the future. We are planning to identify and overcome challenges together with our partners. This is a summary of my presentation. To address pattern scaling by using EUV chemically amplified resist, we have developed a new technology by leveraging synergy obtained through combination of the lithography technology and etching technology. We have developed a new technology for metal oxide resist to be used in high-volume manufacturing with high performance and low cost. The same system can be used both for chemically amplified resist and metal oxide resist, which our customers will find convenient. To address high-NA EUV lithography, we collaborate with the partners to provide advanced coater/developer process solution to be used in high-volume manufacturing of the future generation devices. This concludes the CTSPS Business Unit presentation on technologies for future EUV lithography. Thank you very much for your kind attention. Next, Mr. Wakui, General Manager of ES, will present the latest technological challenges and TEL's activities in etch. I am Wakui. I will present the etching system business. First of all, I will talk about overall strategy for etching systems, where we'll continue making an effort to win PORs for HARC process, high aspect ratio contact process, patterning process, interconnect and contact process, and gas chemical etching process. For MLC and slit of NAND and capacitor of DRAM, we will maintain differentiation in processing performance and productivity. For channel four of NAND, we will introduce new equipment. For patterning, we will promote differentiation through combined etching and film deposition etching collaboration. For the interconnect and contact process, our expertise for logic, which is our strength, will be deployed to DRAM. For the gas chemical etching process, we will expand its applications to new market segment. Let me start with memory business opportunity. We will address business opportunities for dry etching, which is increasingly adopted both in NAND and DRAM. For NAND, as shown in the slide, further multilayer stacking is going on by dividing layers into multiple tiers in processing. Aspect ratio is reaching 70: 1. In order to win PORs in the HARC process, which increases along with the stacking, we will enhance etching performance, address high aspect ratio, and help our customers improve productivity to mitigate their costs. This shows higher stacking of memory devices. As shown on the left-hand side figure, 3D stacking of NAND keeps going. The number of layers is expected to increase further from the current 1xx generation, and accordingly, NAND device will get higher and higher. For DRAM as well, when the current planar structure is replaced by the three-dimensional structure, high aspect ratio etching process is expected to increase, just like the case of 3D NAND. Ongoing 3D stacking will help the etching market keep growing. This slide shows the challenges of the etching process we face, along with the trend of higher aspect ratio. From the left, you can see the etched profile of capacitor of DRAM, channel hole, slit, and MLC of NAND. As aspect ratio increases along with multilayer stacking, there will be more demanding challenges, such as formation of deep vertical profile, control of dimensional variation, and selectivity against underlying layer. As shown in the right figure, a problem of depth loading, which suppresses etch rate at deeper area, has a negative impact on etch performance and productivity. I will talk about our efforts to address these challenges. The figure on the right shows how ions enter deep hole and trench. By making ion incident angle closer to plumb than before, we have enabled ions to reach deeper areas, which realizes accurate processing control and improved productivity. By leveraging this technology, we will win more PORs in the critical processes for which processing of a high aspect ratio profile is essential. Next, I will talk about our efforts to enhance productivity. As I presented in the last IR Day, we introduced new platform, Episode UL, into the market. It features flexibility to select the number of chambers to be mounted. It saves space by reducing footprint, and it realize smart tool through an autonomous process control, including automatic replacement and big data analysis. Episode ULs were delivered to multiple customers this year, helping the customers enhance their productivity. Next, I will present logic business opportunities. In addition to multilayer interconnect process, which is our strength, along with further device scaling, device structure will be varied as shown on the right, and also EUV lithography will be introduced. To address these trends, we will provide appropriate patterning solutions. Today, I will present how we address EUV lithography and gate-all-around nanosheet. This slide shows etching in the EUV lithography. Introduction of EUV lithography drives device scaling, but as shown on the right, the EUV lithography process induces defects and poor local critical dimension uniformity. Since EUV resist film is too thin for dry etching and features poor plasma resistance, there are problems such as poor hard mask performance and pattern collapse in patterning. To tackle with these challenges, we think it's important to complement the patterning process with etching technology. We will merge the film deposition technology and etching technology to overcome the challenges of the EUV lithography. The defects and poor local critical dimension uniformity caused by EUV lithography are addressed by repeating the film deposition and etching process, as shown on the top. Specifically, uniformity of hole size is improved in this case. Mask selectivity in etching process is improved by depositing protection film on the resist, and selectively remove it, as shown on the bottom. We also collaborate with imec and ASML, planning to provide patterning solutions for the future high-NA lithography. This shows how we address the transition of transistor structure from fin structure to nanosheet. As one of the efforts to address nanosheet fabrication process, we are studying the possibility to use chemical dry etching system to multiple applications. In these processes, it's necessary to etch silicon germanium, the black portion in the upper figure, and leave uniform and smooth silicon film untouched. We plan to leverage the chemical dry etching, which can isotropically etch silicon germanium with high selectivity against silicon and suppress surface roughness so that we can win PORs. Finally, I will present initiatives to enhance our development and production capability in the etching business. Last month, construction of Miyagi Technology Innovation Center was completed in Tokyo Electron Miyagi, as we announced. This center aims at creating innovative technologies and drastically enhance productivity. One of the options to achieve this aim is collaboration with our partners. This shows the roles of Miyagi Technology Innovation Center. The center is expected to play the following three roles to promote innovative manufacturing technology in our entire plants. Firstly, Future Tech Incubation Lab is founded to develop technologies that enhance performance of process to component, reduce lead time, and mitigate environmental footprint, as well as to develop new materials. The second role is innovation of manufacturing technology. We built Production Innovation Lab to study DX technologies to sense and analyze field data and explore possibility to use robot technology in assembly. To prepare for increasing demand and raise efficiency, we will develop new production systems and enhance automation of manufacturing lines. The third role is Training Center to provide higher standard training. By leveraging virtual reality and mixed reality, we will organize remote training as well. This is how we can enhance our strength. In this way, we can enhance the strength of the field, not only our company, but also our customers. Here's a summary. Driven by 3D NAND patterning, high level of investment is expected for etching system. Adapting to changes of device and addressing customer needs, we will continue with technology innovation for both memory and logic customers. We will enhance our development capability and production capability to be prepared for the further market growth in the future. Thank you very much for your kind attention. This concludes my presentation. Next, Mr. Ishida, General Manager of TFF, will present TEL's approaches for the next-generation deposition technology. I am Ishida of TFF Business Unit. I'll present our approach to next-generation film deposition technology needs in Thin Film Formation Business Unit. In order to realize next-generation devices with high performance, various changes of device structure are being studied. For logic device, nanosheet is one of the promising options, and all logic device manufacturers are expected to adopt it. On the right, you can see the structure of nanosheet. For nanosheet, multiple very thin dielectric films are essential. They must be resistant to chemicals and feature extremely low parasitic capacitance. Their thickness must be uniform in every direction. We must develop a dielectric film to meet all these requirements. TFF Business Unit is studying possibility to use a batch process. Why batch? We propose batch process taking account of all the requirements. The clear advantage of batch process is its cost advantage and stable film thickness and quality. To control characteristics of the dielectric film, we are also evaluating possibility to use BALON. As we currently think thermal treatment can be used, we are planning to perform the process in batch furnace. Toward the future, we will find a way to expand its applications. In order to expand process options, such as film deposition, etching, and inhibitor of absorption, and in parallel, to maintain good film quality at low temperature region, we are evaluating multi-processes by using single wafer processing. As low-k film may become necessary in the future, we are evaluating new materials in batch furnace, which we didn't conduct it before. We are prepared to cope with future change of the needs and to address more demanding needs. We will compare the batch furnace and single wafer processing system in terms of technological needs and cost, based on which we will provide most appropriate system to the customers. It is our strength that we can start this evaluation project together with the customer at earlier stage and discuss the direction of the new system. Next, I will talk about multilayer stacking, which is a technology inflection point in 3D NAND. As stacked oxide and nitrate film need to be etched multiple times, it is difficult to obtain perfectly vertical profile in trenches and holes to their bottom. As a result, gap width gets varied. Atomic layer deposition features an ideal surface reaction. NT333, our semi-batch system using ALD technology, has been widely used for 3D NAND. In the case of multilayer stacking structure, however, because of its bottleneck profile and bowing, it is very difficult to deposit film without any voids in holes and trenches. To overcome this problem, we have developed a new technique to locally reduce film deposition rate. Specifically, film deposition rate is reduced only at the top of the profile to keep its top open. Then ALD film is deposited. This method can be used in single wafer processing system, but we decided to use semi-batch system because the semi-batch system can increase productivity, and it has been used in high volume manufacturing line. Next, I will talk about new initiative of silicon film deposition using batch furnace. Along with logic device scaling, at the stage just before shift to nanosheet structure, dimensions of fin structure are getting extremely small. Due to the minute dimensions, we encounter the problem of fin structure erosion, and it becomes necessary to introduce a new process to tackle with this problem. Intel will introduce epitaxial growth of sacrificial film. As fin is located at the substrate, the sacrificial film need to feature comparable quality to the substrate. To realize good quality film, we have integrated pre-cleaning process into batch CVD silicon system, which is widely recognized in the market. As we successfully realize the new process by using cost-effective batch furnace, the new process has been adopted in our customers' high volume manufacturing lines. The new initiative of silicon film deposition that I described in the previous slide might potentially have other applications. For example, silicon germanium stacking film used for nanosheet, boron-doped silicon film used as a stopper film in backside PDN, and silicon germanium stacking film used for 3D DRAM. These potential applications, however, are extremely demanding in terms of technology because these films are required to feature outstanding quality. They need to be stacked, and they need to be thick. Having said that, if these films can be deposited in batch furnace, such process will have very high cost advantage. As the batch process with pre-cleaning combined is proven in high volume manufacturing line, we keep working on development to expand these applications. What I will present next is not film deposition, but film quality improvement by means of thermal treatment. High quality film must be deposited to enhance electric characteristics and reliability. It is also necessary to fix damages induced by film deposition process. To overcome these challenges, we are studying various treatment. Today, I will talk about D2, deuterium annealing. This process has been developed for 3D NAND. Through collaboration with the customers, TEL has developed various processes to improve device performance and also develop hardware optimal for process conditions. Since this process performed in batch furnace, it features high productivity and can provide cost-effective means to improve device performance. This is another example of film quality improvement. In the previous case, as 3D NAND features high thermal resistance, batch furnace is adopted. In the case of logic device, however, many processes, except for some front-end-of-line processes, are subject to temperature restriction. There is an increasing need to deposit dielectric film at extremely low temperature. An innovative approach to use plasma treatment to modify deposit film is being actively evaluated. Our product, Super I/O, is one of the promising technologies, as it can generate high density radicals at low temperatures. This technology is now being evaluated. Potential applications of Super I/O includes modification of interlayer dielectric film in nanosheet and dielectric film for subtractive metal interconnect. Depending on technological requirements, we propose batch system, semi-batch system, or single wafer processing system and evaluate it. Here's another technique for film improvement. This uses single wafer processing system. By combining UV lamp and remote plasma, a very thin dielectric film can be deposited. Reaction of reactive species activated by UV lamp is very slow, and therefore, it features high controllability, suitable for depositing thin, high-quality films. This technique has been adapted in high-volume manufacturing line of some devices and by some customers. To address further scaling and oxidation of interface of thin film, this technique might be applied to logic nanosheet and 3D NAND as well. This is a module solution to be realized by using TEL's corporate assets. It is not single effort of TFF. We intend to provide the solution to improve post-etch local CD uniformity by using TFF's EXIM, a PVD system developed for MRAM. This hard mask film, deposited in our PVD process, features higher selectivity than currently adapted hard mask film. The film can be formed at temperatures which CVD cannot handle, and it features outstanding selectivity. We need to evaluate etching performance using this new hard mask. It's also necessary to evaluate removal of film at level, in order to check whether the new hard mask material causes any problems for the integration. We are currently taking cross-BU approach in these evaluations. We also have started sharing evaluation result with the customers. Here's a summary. In the next-generation devices, demand for film deposition technology will be increasing diversified. Though it is extremely difficult to develop new technologies, we are always required to reduce costs. TEL will pursue an optimum solution in terms of both performance and cost, out of many options. We will provide technology solutions by combining the film deposition technology with pretreatment etching and modification. We will expand cross-BU and cross-product collaboration as we introduce at the final portion of my presentation. We will provide an appropriate solution at the appropriate timing by sharing information with the customers in the evaluation process. Our customers agree and support this strategy of TFF Business Unit. New initiatives of technology development are in progress in many fields. We will develop leading-edge technologies and corresponding process tools to raise the customers' trust and expectations and expand our own business. This concludes my presentation. Thank you very much for your kind attention. Now we'll have question answer session till 17:30. We will receive questions both in Japanese and English, but as our attendees are on the Japanese channel, please allow us to restrict verbally asked question to only in Japanese. When you ask question in Japanese, please hit raise hand button on Webex. For details, you are kindly requested to refer to the instructions attached to the email. I will call name of the person who ask a question one by one. Please check the chat box on Webex, as our secretariat will inform you in advance that you will be next person to ask a question. Our secretariat will unmute you when you ask question. If you ask a question in English, please use the chat box to send the question and text, together with your name and affiliation, to the secretariat. We will refrain from answering a question if no name or affiliation is given. On the Japanese channel, I will read out the question translated into Japanese, and our attendees will give an answer in Japanese. While on the English channel, it will be simultaneously translated into English on a real-time basis. For questions verbally asked in Japanese, please allow us to limit one question with one follow-up question. For English questions sent in text, I am very sorry, but we will receive one question without a follow-up question. The first question, sorry. Mr. Yoshida of CLSA Securities, Japan. Mr. Yoshida, please. I am Yoshida of CLSA Securities, Japan. Thank you very much for your very detailed presentation. The first question is about slide 101, WFE investment per 100K wafer starts per month. For logic, in the past, you presented a value for 5- nanometer, JPY 20 billion. However, this time, for 2- nanometer, JPY 21 billion. Because of the efforts of the two vendors, the focus has been revised downward for 5- nanometer to 3- nanometer and 2- nanometer. When look at the investment, the increase is rather mild. The cell graph intensity increases. Some manufacturers have said that. What cost will be reduced according to your prediction? In the past, about 15%-20% increase is expected for investment from one generation to another. I want to understand the reason for memory, NAND, triple stack and 3D DRAM. When they start, what happens to the WFE investment and breakdown by process, too? I want to hear about some future of the memory. Dr. Sekiguchi, please. It's a difficult question. The cost increase is driven by exposure and patterning. I think patterning and exposure lithography accounts for the huge amount of the very big amount of costs. 3- nanometer and beyond, in order to reduce cost, there are various method, combination of various tools to produce the devices that will become more important in the future. For patterning technology, as you heard from the business unit, we are now focusing on the combination of different devices. At the same time, the production technology, the productivity is enhanced where you can reduce cost as well. There is one addition from IR. This is the prediction based on our process flow. This is capital intensity based on our estimations. Customers 3- nanometer or 2- nanometer node are way in future, so they are not fixed one. This is just the estimation prepared by TEL, our company. For memory, in that sense, you haven't produced your own estimated flow yet. Is that correct? 3D DRAM, for example. For 3D DRAM Dr. Sekiguchi, please. For 3D DRAM, actually, it's way ahead, so things are not yet fixed. That's what I said in my presentation on page 92. Key modules, you can see the stack formation, cell transistor formation, capacitor formation, all those area, there is room for technology innovation. As of today, we can just give this number based on current assumptions. Thank you. One follow-up question. Etching technology, slide 130, page 130, Gate-all-around nanosheet, selective etching, gas chemical etching advantage is shown over here. For the wet etching, I think there is another option using the wet etching. What is the difference in cost between the two, and which technology will be more promising at this stage? Wakui-san, please. Again, difficult question again. Technologically speaking, so etching selectivity and high uniformity, we need to pursue those two requirements. That's gas chemical etching. I think that gas chemical etching has some advantage because of those two reasons. Your question is about whether wet etching or gas chemical etching, that is very difficult to answer. We believe there are some processes which only gas chemical etch can handle. Thank you very much, Mr. Yoshida, for your question. Next question is from Mr. Wadaki from Nomura Securities. Mr. Wadaki, please. Thank you very much for very detailed presentation. I learned a lot from today's session. I have a question for etching system to Dr. Sekiguchi and Mr. Wakui. Now we are talking about etcher step, number of stack steps, because what happens for high NA with SPIE, I saw some information for 3- nanometer or 2- nanometer M2 for EUV with LELE. EUV so far in double are to be used. If that's the case, maybe we should use etching system 10 times. You can sell a lot of etchers. After that, all those things will be replaced by high NA. That's a roadmap. All of a sudden, etcher order will be decreased. In the case of 3- nanometer or 3- nanometer high NA for logic etching, how do you view the number of etching processes in logic in 3- nanometer or 2- nanometer by using high NA? For 2- nanometer, 3- nanometer, things are still uncertain in the customer side, but so I think they are gradually come up with some integration flow. In your question, you pointed out the patterning, it's getting more complicated in the beginning, so number of etching will increase. That is the starting point. However, ultimately, customer will adapt in order to reduce device cost, so we need to provide the most simplified process. Integration flow should be designed by using customer's wisdom. Ultimately, maybe number of the processes, a bit difficult for us to give you the number of processes, but we don't see the explosive growth of the etching process when we see the next generation up until N3 or N2. Self-aligned block, I think that require 10 etching process. I think this estimation should be not so wrong. For patterning, maybe Dr. Sekiguchi, please. Mr. Wadaki, could you repeat your question once again, please? I said self-aligned block 2. One block requires four etching processes, and when you carry out two blocks, that requires four etch processes. In addition, you need to carry out LE in advance, so 10 etching processes might be required. I think your estimation is not so wrong. For 3D ReRAM, when 3D RAM will come, and different from etcher, bit line etching, the word line is to be etched, and capacitor is to be etched. The number of etch processes will be increased. I think that will be good news for the etching business. What do you view, Mr. Sekiguchi or Mr. Wakui, for timing? Page 91, slide 91. HBM for 3D ReRAM, 2020, 2026 or 2027. That's the HBM estimation. That's when this 3D ReRAM might appear. The number of etchings processes, it goes vertically in the past, but it go now laterally. Each require film deposition and etching for each layer. The number of process, of course, it depends on the number of capacitor, but I'm sure that the number of process increases. That's true. Thank you very much. Thank you very much for your answers. Thank you very much for your question, Mr. Wadaki. Next question is from Mr. Yamamoto from Mizuho Securities. Mr. Yamamoto, please. Mr. Yamamoto, could you unmute, please? Can you hear me? Yes. I'm sorry. I am Yamamoto of Mizuho Securities. For ESG and tool development, my question is rather vague. I'm sorry for that. CO2 emission, when you think about Scope 3 for CO2 emission, direction of the tool development will change or not? In order to improve the CO2 emission in Scope 3, do you have any idea to include something new in the development process, or the direction, conventional direction remain unchanged, and as a result, the CO2 emissions will be reducing. Some competitors said green, but they try to enhance or appeal their process performance or tool performance. Do you think direction of development will change to reduce CO2 emission in Scope 3? Segawa-san, please. I am Segawa. Let me answer to your question. At present, the productivity enhancement, that direction, conventional direction, is to be pursued. At the same time, we can enhance green. I think we can pursue those two targets at the same time. As I said earlier in my presentation, the regulations are getting more and more stringent, and customer's environment, there are different customer requirement depending on their environment. We need to focus on those situation to decide what to do, what way we need to focus in our development. In the past, do you have the conventional direction of the development and there is no big change in your direction of development? For mainstream development, yes, that's correct. Users, so for green, when they select the tool, are there any users who focus on green? Even if for the critical ones, they cannot prioritize green, but for other area, some users just focus on green when they select the tools. Do you have any information getting from the customers in? I am Kawai. Good afternoon. Right. There are three stages. Tool performance in the ESG CO2 emission reduction for semiconductor device performance, tool performance, and the site activities. We are focusing on those three areas for CO2 emission. From the viewpoint of the customers, for example, low power consumption for device and to merge two devices into one, that thing is required. The green performance, it should be part of the tool performance. That's how we understand and how I'd like you to understand situation. In other words, the per unit area, when a clean room is operating, the device output per unit area clean room, that has a lot to do with the productivity of the manufacturing line. That should be one of the keys in the tool selection done by customers. Within this limited space, how much devices they can produce, that's very big factor in the customer's selection process. At the same time, in our company, concurrent development is now going on, development and production. We are always thinking about the mass production when we design the process tools, because in the future 3- nanometer, 2- nanometer, 3D NAND to 100 or 300 layers era comes, then tool to tool matching and chamber to chamber matching. That requirement will be getting more and more severe. The matching should be considered when we design a new tool. Tool uptime should be increased, yield is enhanced. These things also have a lot to do with the green or CO2 emission reduction. For the customer to establish the fab with lower CO2 emissions, that will become more and more important. Each customer has their own formula for green. They have, I think, green specifications to be one of the criteria for selection of tool, and that is required. Also legal requirement for environment. We need to pay attention to the legal requirements for environment. Chemical recycling need to be considered as well. When we make a proposal to the customer, at the same time, we need to enhance the alliance with our partners. This is how I can answer to your question. E-COMPASS, we have established the new initiative, and that is one of the background why we're establishing E-COMPASS. Thank you very much. That was very clear answer. Thank you very much for your answers. Mr. Yamamoto, thank you very much for your question. One request from us. At present, the simultaneous translation is carried out, could you speak a bit slower for the interpretation? Next question is Mr. Shimamoto of Okasan Securities. I am Shimamoto of Okasan Securities. Can you hear me? Yes, we can hear you. Thank you very much. From me, about the growth story, I heard your growth story now. Up until 2030, for each device, you have the device roadmap. For each process tool up until 2030, what is your expectations for the growth? Could you show me some order of the coater/developer, dry etch, film deposition, cleaning, prover. You have various products. For those different, could you just give me some clue about growth story toward 2030? Mr. Shimamoto, it's the general roadmap. Your question is about general roadmap, or would you like to know about specifics about the process tool specific roadmap? Rather than specific, I want to understand general roadmap till 2030. Logic, memory, you have presented the roadmap for logic and memory. What is your expectations for growth? I want to know which tool has the high expectation for the growth. That's the gist of my question. Sekiguchi-san, please. I think the President, Mr. Kawai, will give you the answer on behalf of the company. The number of processes, from the viewpoint of the number of processes increase, the logic roadmap on page 75. Could you refer to page 75? The FIN structure, front end of line, will be replaced by nanosheet. In this area, film deposition and etching, the CD, the critical dimensions, have been determined by dry etch + dry etch Certas. They were important. Nanosheet structure is a forks heet, so etching proportion growing. At the same time, film deposition proportion also increased. Cleaning. Direct process increased as well in number. I think all of them will be growing, not evenly, but each process increases. Defined patterning will become required. That's the story for logic. As for DRAM, the scaling, device scaling, will get slowed down. That's what I said. On page 91, you can see the roadmap on page 91. The device scaling, the patterning, ArF immersion lithography and EUV lithography will be used more and more. Basic structure remain unchanged. 2026, 3D DRAM comes out, that's when the changes occur. After that, as I said, film deposition and etching are expected to grow. For NAND roadmap on page 95, over here, what is increasing is number of tiers. The number of stacking, the number of layers for stacking. When more and more layers are stacked, the capacity increase. That's what the current structure is. That remain unchanged. Thank you. Understand. For each device, depending on the use, the important process tools are different. Thank you very much for your answer. May I am Kawai, I would like to give some additional answer. As we said before, 2020, the semiconductor device market is about $400 billion. By 2030, JPY 1 trillion or more is expected. For 2030, semiconductor market grows above JPY 1 trillion. Our customers' market, when you look at next decade, the market will be doubled. That's the current situation. When I look at WFE market also has the strong potential for growing. In the future, now there are four products, coater/developer, etcher, cleaning, and film deposition. In those four products, they are our core products, and we are focusing on those four area: higher capacity, higher reliability, higher speed, and lower power consumption. These are a lot to do with the patterning performance, and those four are expected to grow drastically. This area, for our company, they are the core business at this moment. In our company, we have the broad portfolio, plasma technology and pressure control, thermal control, chemical technology, and also bonding technology as well. We have various technologies as well. We are going to provide the technology that customer will need in the future by leveraging our strength. The semiconductor market is expected to be doubled in size. Toward that kind of high potential market, we are going to promote the technology innovation so that we can contribute to the semiconductor market. At the same time, we'd like to expand our business. Thank you very much. That's my additional answer. Thank you very much. That's all from me. Mr. Shimamoto, thank you very much for your question. Next question is from Mr. Hirakawa from BofA Securities. Mr. Hirakawa, please. I am Hirakawa of BofA Securities. I have a question for etching. Page 125. 125. This time, the ion vertical entry, so the ion incident get closer to 90 degrees. That's what you said in your presentation. What sort of TEL's proprietary technologies are employed? If possible, I want you to explain your technology and your competitor technology. As a result, at present, current aspect ratio compared with your competitor, what is your status for the high aspect ratio? This includes my follow-up question, actually. Isamu Wakui, please. For the incident angle of ions are getting closer to 90 degrees. That's what we are working on. As I said in my presentation, as for the direction, that's RF powerful bias of ions. We should reduce frequency and increase power, and also the pulse technology. Out of those options, we try to come up with optimum solution. That is the uniqueness of our company. Our competitors, the comparison with our competitor, actually the information that we have, it's a bit difficult for me to answer to that question. As far as our company is concerned, three technologies are to be combined in the optimal way. This is how we try to differentiate ourselves from our competitors. For technology, it might be difficult to compare your technology with your competitors, but current aspect ratio, could you just give us some comments on the aspect ratio, please? In my presentation, I said 70:1. That's what I said. At present, current aspect ratio specification is 70:1, and we are developing technology to satisfy that specification, and we try to differentiate ourselves from the competitors' technologies to satisfy the aspect ratio of 70:1. I think in the future generation, aspect ratio gets much higher and higher. Working on the current specification for 70:1, and I cannot give you any more answers about the future technologies or future aspect ratio. Thank you very much. Mr. Hirakawa, thank you very much for your question. Next question is from Mr. Yasui of UBS Securities. Mr. Yasui, please. I am Yasui from UBS Securities. My question is about the technology roadmap toward year 2030. 2030 for logic, DRAM, and NAND, you presented the roadmaps toward 2030. As for plan B, for example, there are some game changer device for 2030. Are there any possibility of changes as game changer from 2D to 3D NAND flash memory is putting forward the device? The manufacturer competition changed, and etching demand increased. Five years to come or 10 years come, if this comes, the demand might change. Do you have that kind of potential game changer? That's my first question. Sekiguchi-san, please. Okay. Actually, one after another, I encountered a very difficult question. It is true that floating gate, from floating gate to 3D NAND, when the change occurred from floating NAND to 3D, the change was rather drastic, and customers didn't expect such high speed of change, rate of change. For 3D DRAM, as for 3D DRAM as well, as for the possibility, yes, there is a possibility. We cannot say anything decisive. Technology development, we need to refer to the future technology development. That's first thing. Second one is system integration. That's what I said in the beginning of my presentation, system integration. What we are very active is back-end of line, so various memories are to be embedded. That's the development. We are working hard. For example, memory and logic are embedded together. That type of device hybridization. We have that sort of activities, device competitive edge increases in that way. Now paradigm shift takes place, and maybe in the future, hybrid device might increase. That is another possibility for the future. Thank you very much. My follow-up question is for memory. You talked about next generation memory. There are many of next generation memory, so I think that possibility is a bit behind. You don't think application does not grow so much? At present, the existing devices will continue to be evolved. That's how we view the future. DRAM continues, NAND also continues. However, for FeRAM, PCRAM, MRAM, actually, they are the application for embedded area, and we are working on development steadily. It's a bit bad news, a little bit, but non-volatile memory and also neuromorphic is also included. Thank you very much, Mr. Yatsuda, for your question. Next question is from Mr. Nakanomyo of Jefferies Japan Limited. I am Nakanomyo from Jefferies Japan. Page 115, 1-1-5. The dry resist comparison with dry resist. On the bottom, I can see that the cost and operation benefits, at the same time, performance. Compared with dry process, wet process is more advantageous. That's what you say in your slide. When the device scaling moving on, are there any theoretical limits? Are there any potential for dry resist? Akiyama-san, please. For dry resist, the performance potential or advantages, not only for performance, I think as on page 115, wet is more advantageous. Generally speaking, dry processing, when you use dry processing, the patterns are resistant to the pattern collapse. That's what we said in the past. We are working on wet process development. We are now working on challenges. That's what I said in my presentation. The pattern collapse can be prevented. Even for the future scaling, we try to develop such kind of technology. I said in my presentation, there are some data, as well as the data considered. For the pattern collapse, the wet process performance as good as dry process to prevent pattern collapse. Against dry process, what we are concerned a lot is the pattern collapse when we developed wet process. Up to until when, are there any theoretical limit or something? You mean the wet process can prevent the pattern collapse? In the case of wet process, the surface tension takes place. Surface tension, the lateral force will cause the pattern collapse. If the surface tension is prevented by adding the development process, in the development process, we have additional chemicals coating, where in rinsing process, we have some technology incorporated to cancel, offset the surface tension. We are doing some collaboration with chemical manufacturer. I'm sorry, I cannot say any limit, but this is what we are working on to take actions against the pattern collapse by developing new technology. Thank you very much. My follow-up question is about on slide 38, Downstream CO2 emissions. Maybe similar question to Yamamoto-san. I can see some figures. When I look at figures of CO2 emissions in downstream, I think your products generate CO2 a lot in the use stage. Those figures do not have so much big meaning. For example, depending on the amount of products to be shipped or the number of devices to be produced. When more devices are manufactured, the CO2 emission increases naturally. What users are concerned is the CO2 emission per device or power consumption per device. My question is, those figures reduced? As for KPI, reducing those figures of CO2 emission does not have so much meaning, or how do you view this CO2 emission in downstream compared with your competitors? Mie Segawa, please. Quantitative comparison with competitors, I cannot give you any answer to that. When we sell more products, as you said in your question, the amount of CO2 emission increases naturally, and the customer fab, the CO2 emission increases when they produce more devices. As I said earlier, the power consumption, water consumption, and CF, gas and chemical, if by reducing those consumption, when we convert it to the CO2 emission, we can reduce convert it with CO2 emission with CO2 equivalent. As a whole industry, we can make some contribution to the reduction of the CO2 emission. At the same time, we can contribute to the mitigation of the global warming. Thank you very much for your answer. May I say, I am Sekiguchi, may I add some comments? On page 67, you can see the environmental KPI, on the left-hand side, there is a state figure. You can see normalized KPI metric on the vertical axis, you can see technology node on horizontal axis. What is plotted over here is the performance changes from one node to another, the number of transistor element per transistor element, what performance takes place, or area per transistor, and energy to be consumed for production, how they are reduced, and process cost, and pure water or the pure water consumption. When you look at this figure, the per transistor, 1- unit transistor, environmental footprint impacts are expected to reduce. Of course, when the number of transistor to be produced increase, overall environmental impact increase, when you use the leading edge node, you can reduce the CO2 or environmental impacts as a whole. That's the message that I wanted to convey by using this slide on page 67. This plot might be changed depending on each individual device. This is total cost. This includes all the process costs. Of course, for each product, we have the figures of cost for each product. Cost impacts might be different depending on the type of the process. Thank you very much for your answer. I am Kawai-san. For ESG, CO2 emission reduction. For competitiveness edge of our company, from the viewpoint of the competitiveness. Year 2030, CO2 emission reduction, 30% reduction is our target toward year 2030, when our process tool is in operation. Also, in this area, in this industry, these figures or targets are the highest compared with other competitors. Among the goals announced by other competitors, this is the highest level of the goals. Importance, semiconductor WFE, semiconductor wafer fabrication equipment. That has a lot to do with the competitive edge. For each product, the productivity is enhanced at the same time. For patterning, other than our company, the number of processes than our process, for example, EUV lithography process. When we propose some idea to contribute to EUV lithography, we want to come up with some solution in terms of environment, cost, and production. I would like to work on those areas as well. I'm sorry, this is my additional comments to you. I am afraid I didn't answer to your question properly. Thank you very much. I'm sorry my question was not so well organized. No, no. Thank you very much for your good question. Thank you very much, Mr. Nakanomyo, for your question. Next question is from Mr. Ishino of Tokai Tokyo Research Center. I am Ishino from Tokai Tokyo Research Center. My question is slightly different from technology, but generally speaking, 5- nanometer foundry logic price is about JPY 15,000, 3- nanometer JPY 25,000. The chip manufacturers, the chip cost is about JPY 50-JPY 80, about 60% increase in chip cost from the viewpoint of the IC manufacturers. Ultimately, the semiconductor supply tight and end user, the consumers, pay more through the cost transfer. About 60% increase will have the impact on the final retail price. Now in today's presentation, 3- nanometer, and you talked about EUV lithography as well. At the same time, on page 115, cost of wet process using metal oxide resists is one third of cost of dry resist process. The 3- nanometer foundry cost increases, then high-NA lithography needs are putting forward or metal oxide resist from the initial estimation. The needs for metal oxide needs are appearing faster or sooner, and many other companies are emphasizing their effort on metal oxide resist. There is some breakthrough in cost. Which product is more affected? One third, are there any drastic reduction costs by introducing cost? Could you just explain that sort of cost trend, please? Thank you very much for your question. Akiyama-san, please. On page 115, this figure. As for this figure, I would like to give you a more detailed explanation on this figure on page 115. You said three times. The major difference is, as you know, the coater/developer at present is connected in line with EUV lithography system. Therefore, after resist is coated, the exposure and baking and development. For that process, they are connected in line. All those four process steps are completed within the in-line system. Compared with that, when we use the dry process, the CVD tool used for the resist film deposition, and after that, cleaning process is necessary to clean the wafer. After that, wafer comes into the exposure system. After that, wafers are transported to another system for baking. After that, the dry etch is conducted, and after that, cleaning needs to be conducted. As I said now, there are five or six more additional processes are necessary in the case of dry process. Those additional processes are major factors of the three times difference of the cost between wet and dry. Another thing you just asked me, high- NA lithography. As I said in my presentation, imec, ASML, together with those two organizations, we are now evaluating technology in joint laboratory that will start from 2023. When this technology will be used in the mass production, maybe from N 1.4 or beyond year 2025 or 2026. That is the fastest timing, and I don't think that will change. metal oxide resist application, the metal 30- nanometer pitch and beyond, the metal oxide resist will be actively adopted by our customers. That is the general trend among our customers. Thank you. Thank you very much for your answer. My follow-up question is, ASML IR day the other day, high NA 2025, these are five units to be shipped. According to your presentation, year 2026 and beyond, high NA lithography is not to be used for the mass production, where large amount of metal oxide resist will be used beyond 2026. Is that correct understanding? Existing EUV lithography system is about JPY 20 billion. High NA EUV is JPY 30 billion for one unit. In such a case, your process also, process tool price increased by 50%, just like the lithography system. That will not contribute to the cost conservation or cost saving. Could you share your idea with us, please, on those two points? Your first point, as for your first question, from imec announced some information. As I said earlier, 2023, EUV in enough high- NA EUV system started operation. They are going to develop technologies to install that to the high-volume production area for three years. Against that, ASML, TEL, and the chemical vendors are supporting that technology. Year 2026 is the target year. Conventional EUV lithography innovation speed, I think that three-year plan is rather aggressive plan. When it comes to price, from our company, we are not able to give you any comments on price. One thing for the coater/developer, as far as coater/developer is concerned, as I said earlier, wet process, for this wet process, the chemically amplified resist, metal oxide resist, those two can be processed in one system, one equipment, which is rather unique. Our system can handle both, the number of module increases. Compared with the process, only processing chemical amplifier process, compared with that configuration, the process tool price is expected to increase slightly, it depends on the configuration or specification of the process tool, which affect the process. I cannot say how many% of the increase is expected. I cannot give you any specific numbers. One more follow-up answer. High- NA EUV are not to be used for all layers. Even if we say High- NA EUV is introduced, maybe several layers for this first node. It does not mean they need to invest several hundred billion JPY for additional investment. Including front-end and back-end, it depends on devices. There are tens of layers, and not all of them will use the High NA EUV lithography. The cost increase, how do you think about cost increase? Could you repeat your question once again, please? From 5- nanometer to 3- nanometer, foundry cost is expected to increase. How do I need to understand that? From the processor vendor, you don't see that as a big problem. Is that correct understanding? The foundry cost. Yes, please. 3- nanometer foundry cost or price. The set manufacturer and fabless company to be the manufacturing are contracted out to the foundry. When foundry receive the manufacturing from fabless, maybe that should be JPY 15,000 for 5- nanometer. When it comes to this 3- nanometer, the price goes up by 60%. Does that affect your business as the tool vendor? For the node, for example, 3- nanometer, the cost is so and so. For our customers, designer and integration methodology, depending on the choice of the design and integration techniques, the cost is different, so we are not able to give you any comments on that regard as a tool vendor. As I said earlier, when we increase the productivity of process tool or enhance the yield, this is how we can support our customer to reduce their production and manufacturing cost. I am Kawai. For semiconductor, now we are shifting from the product to the value. Semiconductor used to be the rice of the industry, the essential building block of the industry, and high-end area. High value added. The added value is increasing higher and higher. In order to realize some solution of value, this technology is essential in that area, critical area. As for the process tool vendor, of course, we are working hard to enhance productivity and yield enhancement. We try to pursue the technology innovation, which is essential for us as a tool vendor. We provide the values, and customer can recognize that sort of values sufficiently. For the customers, we are supposed to reduce costs, that's not the story. In digitalization and green, digital and green, we try to contribute the dream-inspiring society. I think we can provide sufficiently high added value in our business environment, and there is a huge growth potential. The technology innovation in semiconductor continuously will accelerate it, according to my understanding. As Sekiguchi-san said in the beginning, the high-power MOS area, for that particular area, there are legacy nodes to be handled. In that area, high-power MOS area, the cost reduction or price reduction is the best options. Our Field Solution business contribute a lot there. This is not the concern, but we think there is a huge potential for growth about your question. Thank you very much for very thorough answer. Thank you very much for your question. Now it's time for us to close the session and thus close the Tokyo Electron IR Day. For those questions we are not able to answer today, we will upload answers to Q&A page of our website. If please send the text of the questions if you want to raise questions in text. Thank you very much for joining us this virtual visit schedule today.