It's time for us to start Tokyo Electron IR Day. Thank you very much for joining us today despite your very busy schedule. I am Yatsuda of IR Department, serving as the moderator of today's session. As we reported in the last financial announcement, the WFE market in 2025 is expected to be $110 billion in size, comparable with 2024. As you know, compared with other industries, the semiconductor industry features drastic market volatility. Since the end of the 1990s, when the Internet started to spread to the early 2000s, when the IT bubble burst, this volatility has been called the Silicon Cycle. Since the late 2010s, when investment in data centers came into full swing and IoT became the social infrastructure, semiconductors have become increasingly important. The market growth in that period, which was more rapid and secular than before, was named Super Cycle. As you all know, the semiconductor industry is currently in the adjustment period due to the backlash of Super Cycle, along with the spread of AI application. The industry is expected to grow further in the longer term. Today, we will present our company's business opportunities and growth potential, looking ahead beyond the current midterm management plan, whose target year is fiscal year ending March 2027. Before starting the presentation, let me explain the flow of today's session. We will make a presentation for about 90 minutes. For the agenda and speakers, you are kindly requested to refer to IR Day presentation materials posted on our website. After all presentations are completed, we'll take a short break and move on to the question-and-answer session. We are planning to close today's session at 6:00 P.M. Japan time. Though we will speak in Japanese today, this meeting uses two channels of Zoom for simultaneous interpretation between Japanese and English. You can use telephones to join this meeting, but you are kindly requested to use apps on PCs or mobile terminals if you want to watch video, play during the presentation, or plan to ask questions. Since this meeting is intended for institutional investors and analysts, we would appreciate your understanding that we receive questions only from institutional investors and analysts, as usual. We will post the audio contents of this meeting in Japanese and English on the website within a couple of days. We'd really appreciate it if you could also visit our website. So, first of all, Kawai, CEO, will present semiconductor market outlook and TEL's growth strategy. Good afternoon. I am Kawai. Once again, thank you so much for joining us despite your very busy schedule. As shown here, I will talk about the semiconductor market outlook and TEL's growth strategy. It has been some time since people first started to use the term VUCA. In fact, various things, including rainstorms, floods, the increase of heat strokes due to extremely hot weather, and pandemic threats, have a significant impact on our way of life and working. Amid these circumstances, to build a strong and resilient society which keeps economic activities going under any situation, it has become a good global mega trend and common value to accomplish both digitalization and decarbonization for global environmental conservation. Green by digital is to make the social system itself efficient and realize green society by leveraging digital power, and green of digital is to promote energy conservation of digital infrastructure such as data centers. The effort is essential to accomplish both of those two is semiconductor. Our company manufactures equipment to create semiconductors. Looking back the past 10 years, we have achieved an exponential growth. Comparing the result of the fiscal year ended March 2015 and the financial estimate of this fiscal year, while the WFE market grew by 3.1 times, our net sales increased by about four times, operating income increased by about eight times, and net income attributable to owners of the parent increased by more than seven times, significantly outperforming the market growth. The driver of such achievement is growing semiconductor demand triggered by the first wave of the ICT industry, namely technology innovation of IoT, cloud computing, edge computing, and Industry 4.0, and now we are in the era of the second wave. The technology drivers of the second wave include AI, AR, VR, and autonomous driving. Along with the arrival of generative AI, semiconductor demand is growing more and more. With the backdrop of this trend, the semiconductor market is expected to grow furthermore. According to the preliminary WSTS report, the semiconductor market size exceeds $600 billion in 2024 for the first time. According to IBS, American market research company, the semiconductor market is expected to grow to about $1.3 trillion in size in 2030. Since the invention of a transistor, it has taken more than 75 years for the semiconductor market to grow to the current size. Virtually within five to six years to come, one more market with the same size as the current market will be created. But this is not the end of the story. Technology innovation will never stop. The demand for computing will keep growing in the future. Accordingly, the communication infrastructure to support computing will also evolve. Quantum computing implementation of 6G and 7G will create the third wave, and the semiconductor market will grow furthermore. According to SemiAnalysis, the semiconductor market is expected to grow to $5 trillion in 2050, which is eight times bigger in size than the current semiconductor market. The semiconductor market has an extremely big growth potential. Tokyo Electron Vision is a company filled with dreams and vitality that contribute to technology innovation in semiconductors. We are pursuing technology innovation of semiconductors which supports sustainable development of the world. Believing profit is a measure representing the magnitude of value of a production service, we will seek profit to lead to investment for next growth, and it is people that realize our vision. Respecting engagement with all of our stakeholders, we consider our employees are the source for value creation. This vision is based on the concept of CSV, creating shared value. The CSV is that the company leverages its expertise to overcome social challenges, which creates social and economic value and facilitates corporate value enhancement and sustainable growth. To support the realization of digital and green through our contribution to semiconductor technology innovation, we are determined to provide production service with both technological and social value so that we can pursue sustainable growth. We name it TSV or TEL Shared Value, based on which we are implementing business activities to pursue sustainable growth. To realize this vision, in our midterm management plan, we set the financial goals to achieve net sales of JPY 3 trillion or more, operating profit margin of 35% or more, and ROE of 30% or more by fiscal year ending March 2027. As a manufacturer, we will generate operating income of more than JPY 1 trillion and outperform the market growth to lead to further business expansion of our company. To realize digital and green that I mentioned in the beginning, semiconductors are required to feature higher speed, larger capacity, superior reliability, and lower power consumption. To fulfill these requirements, there are two approaches taken by semiconductor manufacturing. The first approach is scaling, which is well-known intrinsic nature of semiconductor evolution, increasing density of transistors on chip. The other is heterogeneous integration, which is a technology to integrate multiple chips and functions on one package, such as a combination of processors and HBMs. A typical example leveraging both scaling and heterogeneous integration is AI semiconductor. Realization of AI semiconductor requires a front-end process and advanced packaging process. For the leading semiconductors, the direction of technology innovation shown here is expected in the future. For example, in the case of logic device, introduction of CFET structure in transistor, adoption of backside PDN or backside power delivery network, and integration of chiplets are expected. For DRAM, adoption of VCT or vertical channel transistor structure, introduction of 3D DRAM, and evolution of stacked memory, including HBM, are expected. The technology innovation is perceived at furious speed. Our broad product portfolio can fully cope with such technology innovation. Our products have a particular strength for the front-end process to realize scaling, while we are actively providing solutions for critical advanced packaging by leveraging expertise accumulated in the front-end process. This shows the research of TechInsights. It shows the WFE market. As you can see, the WFE market, which has constituted the majority, is expected to grow continuously at an annual rate of 10% in the future, to grow by 1.8 times in six years to come by the year 2030. In terms of growth rate, the test and assembly market is also expected to grow with a CAGR of 13% to be doubled in size by 2030. This slide shows the highlights of our company in this fiscal year. In this fiscal year alone, there are so many items that were newly adopted by the customers or started joint development with the customers. In order to steadily introduce these pieces of equipment into the customers' mass production lines, we will continuously make investment. Last year, we announced this five-year investment plan, as you can see here. At present, we are implementing this plan steadily. This is the investment for the future beyond our midterm management plan. To cope with the rapidly expanding market, our production volume is expected to increase comparatively. Taking account of the work-life balance of engineers, digital transformation, leveraging AI and robotics will be essential for the manufacturing process. I'd like to share with you the video showing the image of what will happen in the future. With such a future of manufacturing digital transformation and robotics in mind, our factories will facilitate further evolution. As a first step, we have decided to build a new production building in Tokyo Electron Miyagi, as we announced before. Based on the smart production initiative to realize next-generation manufacturing concept, the new production building will adopt automation of logistics function and manufacturing process. We will aim to increase labor productivity by four times, double space efficiency, and reduce production lead time by a factor of three compared with the current level. Looking forward to the future, we have redefined our materials as shown over here. To become a truly global excellent company, we will steadily proceed with our initiatives. A prosperous future that will be realized by semiconductors. The semiconductor market, to support such a future, has entered a new phase of growth. To build a strong and resilient society which keeps economic activities going under any situation, we will fulfill our vision, a company filled with dreams and vitality that contribute to technology innovation in semiconductors and execute our corporate philosophy. Toward the world number one, Tokyo Electron will continue to take on new challenges and keep evolving to create and deliver high-value-added proprietary technologies that no one has ever seen. We will make an effort to always be a company with dreams and vitality, being beloved and trusted deeply by our stakeholders. Thank you very much for your kind attention. Next, we'd like to invite Mr. Kawamoto, Division Officer, to talk about elevating the financial position and points for future growth. Hello. This is Kawamoto in charge of finance. So from my side today, I would like to talk about the elevating financial position and points for future growth briefly. This slide indicates net sales and gross profit margin trend from FY 2015 to FY 2025. As Mr. Kawai explained, over the past 10 years, we have largely outperformed the WFE market in terms of growth. Net sales has grown at 15% CAGR, and gross profit margin arose significantly on high-value-added products and improved production efficiency. As you can see, gross profit margin has increased about five points from 40% to 45% approximately. Future technology and products, as well as the initiatives for the new production building in Miyagi announced on the 6th of February, are key for further improvement. After myself, the business side will present these topics. Today, it is a great opportunity, so I hope that you will hear what I have to say. Next, this is the situation of the capital investment and cash flow. Our industry, known as the semiconductor market, we are continuing aggressive capital investment. As for the R&D expenditures, at the left top, we will invest JPY 254 billion in this fiscal year. And since FY 2020, we have been expanding the investment at 16% CAGR. And as you can see in the purple bar chart, we are also trying to improve development efficiency as well. At the left, we will make a JPY 170 billion investment. Most recently, because of the construction project and so on at a subsidiary and so on, as I was introduced earlier, we will be working on a major project such as the new production building in Miyagi. This is essential for our growth, and so in these projects, we will be deploying our cash to a great deal. On the right-hand side, this is the cash flow. The cash flow situation is quite favorable. This is supporting our growth investment, and also, I'd like to talk about the shareholder return trend from here on, so a basic payout policy is that 50% of the net profit will be allocated for the dividend payout. And as far as share buyback is concerned, we are making a flexible consideration. Based on this policy, you can see the situation of the shareholder returns based on the payment date on the chart. In the last fiscal year, that is fiscal 2024, we conducted a shareholder return exceeding JPY 300 billion. And in FY 2025, this fiscal year, it will be close to JPY 400 billion. Looking at the free cash flow, which is in the bar chart, the shareholder returns is more than 100% on average since March 2020. And we are in the same league as our major global peer group. We will continue to aim for continuous high level of cash generation and shareholder returns. Finally, this is the summary of what I've just explained today. With the provision of high-value-added products and productivity efficiency enhancement, we will elevate gross profit margin and aim for a high-level cash generation. Furthermore, we will continue aggressive gross investment and shareholder returns and boost our corporate value even more. That is all for me. Thank you very much for your kind attention. Next, Hiroshi Ishida, Division Officer, will give us a presentation on opportunity in front-end process business and activities in digital and green. Good afternoon. I am Ishida, Front-End Process Business Division, Tokyo Electron. Today, I will talk about our business opportunities in the front-end process and our effort for digital and green. The semiconductor market has been growing, driven by numerous innovations. In the semiconductor market, which is expected to grow further, we will keep promoting innovation by leveraging our leading-edge technologies so that our company can make stronger contributions. In the semiconductor market, which is expected to grow to $1 trillion in 2030, AI-related devices account for more than 70%. However, it doesn't mean that the spread of AI-related devices will automatically drive the market growth. In the market growing to $1 trillion or more, we must address various challenges, including provision of equipment featuring extremely high productivity, labor shortage, cybersecurity, safety, and net zero. This shows the equipment market trend. Compared with the test and assembly market, the WFE market has been larger in size and is expected to grow at an annual rate of 10% to be double in size from 2023 to 2030. For advanced logic and DRAM, whose growth will be driven by AI, the time of each system will increase with a higher growth rate. Film deposition for advanced logic is also expected to grow rapidly. A large number of new products that our business unit general manager will present today will enable TEL to expand SAM and outgrow the WFE market. I will talk about technology inflection points in the technology roadmap and touch upon opportunities of our business penetration and growth, leveraging our technologies. This shows the logic technology roadmap till 2038 based on our focus. As shown here, logic scaling is continued through innovation of structure and materials of transistors. Further device scaling requires more precise control of film deposition and etch process. More complicated transistor structure will bring a big opportunity for gas chemical etch business. Along with interconnect scaling, there will be emerging needs for new materials such as ruthenium and new structures such as air gap. For lithography, high-NA EUV lithography will be introduced to be used together with multi-patterning. MOR metal oxide resist will be adopted. This is DRAM technology roadmap based on our focus. 2D DRAM scaling will continue using 6F squared cell structure at least until 1d node or 10 nanometer node. This will continuously increase aspect ratio of capacitor structure, which will raise the difficulty of etch process. To improve capacitor capacitance, continuous technology innovation for film deposition will be required. To further enhance bit density, a new structure such as 4F squared vertical channel transistor will be adopted in three nodes from 1a node. Beyond 1d node, 3D structure will be introduced. In the 3D structure, needs for film deposition, etch, and gas chemistry are expected to grow significantly. This shows NAND technology roadmap. The number of layers stacking will increase by 1.3 times every 18 months. In 2030, more than 1,000 layers will be stacked, and the height of memory will exceed 40 micrometers. To realize this structure, technology innovation to etch high aspect ratio hole and slit will be essentially required. It's also necessary to apply molybdenum to word line and lower channel silicon resistance. As I said so far, along with market expansion driven by AI-related devices, further device scaling is expected to continually add higher values. By addressing these technology inflection points, Tokyo Electron will have stronger growth potential and opportunity. In the following presentation given by each BU general manager, our technology advantage will be described in detail. Tokyo Electron will keep providing production service to bring high value added to the customers and the semiconductor industry. High value added value is expressed simply in this slide, which will support sustainable market growth to enhance yield and throughput and raise process accuracy to lower the number of process steps, running cost of FFF, and environmental footprint. Towards sustainable growth of semiconductor market, we believe digital and green will play an important role to overcome challenges, and accordingly, we will accelerate our efforts. When it comes to digital transformation in semiconductor manufacturing, what specifically will be possible? Digital transformation will raise efficiency to the ultra-high level in such aspects as equipment process development, equipment startup, process building, manufacturing process, and provision of service to support productivity enhancement. Digital transformation is also expected to make a strong contribution to improve efficiency in new technology development, to address technology inflections. Self-diagnostic function and automatic maintenance using material informatics, process informatics, and sensors, as well as AR and VR, will be utilized at every aspect of equipment lifecycle. The technology shown in the previous slide includes those which are already implemented, but the slide shows technologies for the near future. Along with semiconductor market expansion, more and more people will be required to install the startup. A large number of tools, equipment maintenance needs will keep increasing even if maintenance frequency is reduced since the install base will grow steadily. Needless to say, we will further increase people equipped with knowledge and experience, but we must avoid situations where our growth is restricted by labor shortage. To tackle this challenge, we are trying to use smart glass to support startup and maintenance staff working in clean rooms by experts, simplify equipment startup procedure, and replace manual maintenance work with robots. We also innovate our equipment manufacturing lines itself. Tokyo Electron Miyagi shown here is a site to develop and manufacture etch systems. We have decided to construct a new production building there to complete construction in 2027. This new production building will adopt a smart production concept to raise efficiency by effectively utilizing data gathered from development through manufacturing operation and introduce automated manufacturing process. We also aim to address the needs of the ever-evolving semiconductor industry in a timely manner to improve product and operation quality. In Miyagi site, ever since its start back in 2011, we have increased production volume by four times by introducing flow line, optimizing takt time, and automating warehouse operation. As a smart production concept will be adopted this time, we plan to enhance capacity by more than three times and raise production efficiency by more than four times. In this new production building, we will implement man-machine collaboration by introducing robots into the manufacturing process. Here are some components of the smart production data solution, robotic solution, review of product architecture. This slide summarizes the growth strategy of front-end process business. Tokyo Electron aims at further growth with front-end process tools, which are sold in large volume. We will release new products into AI device-related areas featuring high growth potential. We will provide high-value-added equipment, leveraging our technology to address technology inflection points. With digital and green, we will support sustainable growth of the semiconductor market. We will facilitate the introduction of high-productivity equipment as well as technologies to save manpower, process steps, and energy. By introducing digital transformation and robotics, we will enhance productivity and profitability of semiconductor manufacturing. With smart production concept, we will raise productivity and profitability of semiconductor production equipment. Thank you very much. That's all from me. Thank you very much for your kind attention. Next, I would like to invite Yasuhiro Washio, VP and General Manager of CTSPS BU, to give a presentation titled "Activities in Coater/Developer and Cleaning System." I am Washio, in charge of CTSPS Business Unit. Today, I'd like to give a presentation titled "Activities in Coater/Developer and Cleaning System." First, I'd like to talk about the process of technology using a coater and a developer system and talk about the cleaning system that is newly under development. First, I'd like to talk about a coater/developer, so I'd like to introduce the characteristics of our EUV lithography coater/developer system, CLEAN TRACK that is used for EUV. Currently, device manufacturers are demanding more smaller nodes to pattern formation technology, and to respond to that, EUV lithography technology is necessary. So this coater/developer system enables EUV lithography process. The strength of this equipment is high reliability, productivity, and versatility, and as inline equipment, it maintains a high share. Over the past 10 years, we have a track record of shipping more than 3,000 systems for lithography with various light sources called LITHIUS Pro Z platform, and it has a high throughput capability and quick processing, and it also comes with EUV response capability. This graph talks about the number of lithography layer accounts for future logic and DRAM devices. Non-EUV lithography indicates CAR or chemically amplified resist, which uses light sources other than EUV, such as i-line and KrF, as well as EUV CAR and metal oxide resist, MOR application layers. In logical devices, from A10 device generation, MOR will be applied, and after that, with device scaling, the usage ratio will increase. In DRAM, from D1B device generation, MOR will be applied, and after that, usage ratio will go up temporarily, but because of the structural change, usage ratio will come down. Competitors are promoting a dry resist system, which can respond in the form of MOR only, but our coater/developer system can work with EUV MOR, but not just limited to that, but including CAR, we can respond to all resist processes. Next, I would like to talk about initiatives around MOR, metal oxide resist, and related efforts. As an example, I would like to talk about development technology for MOR. In the conventional wet development, there is a challenge of resist pattern collapse, and through optimization, improvement can be made, but considering the future device generations, further improvement is necessary. We recognize that as such, we are advancing development of ultimate wet development based upon CLEAN TRACK technology. This table summarizes the comparisons of performance among newly developed ultimate wet development technology, conventional wet technology, and alternative technology that is promoted by competition. The characteristics of the ultimate wet development technology are that it can leverage atmospheric process, which is the strength of the conventional wet development technology and uses a chemical solution compared with the alternative technology advocated by competition. The throughput is four times higher, and also it can reduce the chemical solution consumption by 50% and has a major improvement for pattern collapse performance. On top of that, it can be embedded on the CLEAN TRACK platform that we have. So this technology is an ultimate way to develop technology considering mass production, and it realizes high process performance and high productivity, and it can make contribution to the mass production of MOR process on the part of customers and key customers expressing high hopes for this technology. And customers are already advancing evaluation on their sites. Next, I would like to talk about pattern collapse separation performance data in the ultimate wet development technology. As you can see, thanks to this ultimate wet development technology, major improvement is observed in the collapse separation performance of resist patterns. In the conventional wet development, at 10 nanometers or so, pattern collapse happens, and a number of defects increases, but in the ultimate wet technology, it is possible to restrain collapse down to 8 nanometers or so. Anything smaller than that will lead to disconnections of patterns, so it implies that the collapse is suppressed almost to the limits of resist resolution, and by applying this technology, we believe we can solve the pattern collapse issue, which has been a traditional challenge. Now, on CAR or chemically amplified resist technology, this continues to be key technology for EUV lithography. In CAR, the collapse of smaller patterns is a challenge, just like in the case of MOR, but by adopting a newly developed rinse process and new under layer, you can see the process window has been widened. The number of defects increases for anything smaller than 11 nanometers. A pattern disconnection is observed. This also implies that in the case of CAR as well, the collapse is suppressed almost to the limit of resist resolution, and if I could repeat myself, in CAR as well, we can resolve the pattern collapse issue by combining a new rinse process and new under layer. So together with the MOR ultimate wet development, this technology can be processed in the same system, so we can provide a high level of productivity here. To realize a smaller patterning in collaboration with customers as well as patterning technology partners, we'd like to continue to provide a leading-edge coater/developer process solution. Next, I'd like to talk about a cleaning system. Here, I would like to introduce initiatives and efforts on development of cleaning systems, so we have 300-millimeter cleaning systems. On the left, we have a wet bench, in the middle, a single-wafer cleaning system, and on the right, this is a scrubber, and in these key cleaning system categories, from the viewpoints of both productivity and environment, to deliver new value to customers, we are developing systems and technology. In wet bench, 50-wafer bench was the industry standard, but with the large batch, which can increase the capability or capacity of a batch, we are making a proposal about improvement of productivity and environment. As you can see in the graph, productivity doubles, and we can make a large improvement to water and power consumption as well. In the domain of a single-wafer system, normally SPM is used, which is a mixture of sulfuric acid and hydrogen peroxide, but by adding water vapor, more efficient chemical reaction can be leveraged, and processing temperature can be higher, and as a result, we can reduce the consumption of SPM. So we are proposing this SPM vapor technology. As you can see in the graph, processing time is reduced by 30%, and chemical consumption can be reduced by 50%. In the domain of scrubbers, in general, up to this point, the processing modules were separated for front-side cleaning and back-side cleaning, but we've developed a system where one chamber can clean front and back sides at the same time. In so doing, we realized productivity grows by 100% as well as 30% of COO reduction. Also, I would like to introduce a new system with a concept that is largely different from a conventional cleaning system, so in the cleaning system, we have system domains, namely wet bench and single-wafer cleaning, so both have unique characteristics. Currently, we are developing Cellesta, which is a hybrid system which can realize a combination processing of both wet bench and wafer cleaning, enjoying both characteristics. Target application is, first of all, the process that requires advanced wet etching and advanced drying technology all at the same time. We have gained experiences of wet etching performance through wet bench as well as drying technology with a single-wafer system, and eyeing supercriticality as well. We are making a proposal to the market. Also, going forward with the structure change of DRAM, just like 3D NAND stack horizontal wet etching, application will increase here, so we'd like to target more applications in this area. Also, not just advanced drying technology, but there is a process which requires both high productivity and cleanliness of the surface, so we believe that we can provide a new value with this hybrid system in some domains. So we are developing a technology in this cleaning system business without being bound by the conventional system segment. We'd like to take on a challenge of delivering a new value and contribute to the technology development on the part of customers. Thank you. So next, from Etching System Business Unit, General Manager Nishihara will give you the presentation, "The Latest Technological Challenges and Activities in Etch." Good afternoon. I am Nishihara, Etching System Business Unit General Manager. I will report the latest technological challenges and our activities in the Etch business. At present, NAND, DRAM, and logic require various technologies for etching. To support evolving devices, sophisticated etch technology is essential, specifically for 3D NAND. Deep hole or macro/micro must be etched at high etch rate. For DRAM, capacitor with narrow pitch hole must be etched effectively. Also, by using EUV lithography and multi-patterning, we should address higher-order features. To address high-bandwidth memory, the number of interconnect layers is required to be increased. For logic, to address the structure in the vicinity of gates, sensitive etch technology needs to be introduced. By providing the etch technology to address these needs, Tokyo Electron will win numerous POR and pursue number one market share. In etch process, plasma is excited by feeding process gas into a chamber and applies RF or radio frequency to generate ions and radicals. These ions and radicals are led to the wafer surface. To realize ideal profile in etch process, as shown on the right, it is critical to maintain appropriate ion energy and perpendicularity in incidence angle. It's also important to appropriately control radical species and amount in order to etch oxide film to underlying film while maintaining mask integrity. Along with device evolution, there are more trade-offs in etch process. In the conventional process using fluorocarbon gas, when there are too much protecting materials on the surface, opening gets smaller or clogged. On the other hand, when protecting materials are not enough, mask selectivity ratio goes down or opening profile is deformed to induce oblique ion incident angle, which causes bowing of etch profile. In order to achieve the device evolution, it was necessary to overcome these challenges. Tokyo Electron developed HAR process using new rectangular wave RF technology to control ions. This is a technology to maintain vertical ion incidence angle to achieve ideal etching. HAR stands for high efficiency rectangular bias. This technology is designed to overcome trade-offs of the conventional process. By using rectangular wave RF, energy efficiency on the wafer is improved significantly, and the environmental performance is also enhanced. When using conventional sine wave RF, ion incident angle is varied, which results in bowing problem in high aspect ratio profile etch. By applying HAR technology, which uses rectangular wave RF, ion incidence angle is verticalized to realize ideal etch. By combining cryogenic etching and novel process gas, we have developed a new etch technology, which features high etch rate and surplus deposition on the wafer surface. This new technology is named PHast IE, which stands for phosphorus hydrogen-based fast ion etch. Our customers highly value this new technology as it can effectively overcome the trade-off caused by the conventional fluorocarbon gas process. In this PHastIE process, by using a new process gas and new chemistry, deposition at the opening can be kept limited, while cryogenic process effectively protects side walls during etch process to reduce bowing and make etch rate faster. As a result, high aspect ratio etch performance has been drastically enhanced. Tactras, the etch system that we released adopts HAR technology and the PHastIE technology, and is also able to effectively etch channel holes in the most critical process of NAND, that is, channel holes. Tactras features outstanding process performance, etching depth of more than 10 micrometers with 2.5 times faster etch rate. As its energy efficiency is extremely high, [TeleVAS] can achieve both excellent process performance and environmental performance, and it is adopted by many NAND customers. Combination of HAR technology that we talked earlier and novel gas chemistry such as PHastIE can be applied not only to NAND process but also other various device process to deliver high process and environmental performance and support our customers' technology inflection. For example, when etching DRAM capacitor, the HAR technology makes it possible to etch extremely fine and high aspect ratio profile. For gate silicon process for logic, it becomes possible to remove residual silicon at those positions where conventional technology was not able to, by which device performance is improved. We believe it is our mission to deploy newly developed ideal etch technologies to various key processes. We are developing these new technologies by leveraging the comprehensive development ecosystem, which embraces our company, our suppliers, and universities. By working on such technology development, we believe we can create new ideas and enhance our technological competitiveness, particularly in the field of development of new gas chemistry and HAR technologies. We will leverage this ecosystem to pursue continuous technology evolution, with Miyagi Technology Innovation Center at Tokyo Electron Miyagi playing a core role while we continue active development. The etch market is expected to be doubled or tripled in size in five years to come. While expanding our market share, we need to further enhance production capacity in order to ensure stable provision of etch systems. The new production building to be completed in 2027 does not solely aim at capacity enhancement. It will realize next-generation production model based on the smart production initiatives. Needless to say, initiative includes automation of logistics function and manufacturing process. To realize high productivity and quality, even in the stage of equipment development design, we need to be aware of smart manufacturing concept. To this end, the equipment development and design team should work closely together with the team to build manufacturing system in the factory. We will integrate development sites and manufacturing sites in Miyagi to realize concurrent engineering and advanced production technology. It is our mission to develop etch technology beyond our customers' imagination and deliver them in a timely manner. Today, I talked about etch and PHastIE as an example of new technology development, leveraging the collaboration with our suppliers and academia. We will keep working to increase our market share by meeting customers' expectations and strategically enhance our production site to cope with business expansion. That's all from me. Thank you very much for your kind attention. Next, we would like to invite our VP and GM, TFF BU, Mr. Shigeki Nakatani, to talk about business strategy in thin film deposition. I am Nakatani, in charge of the Thin Film deposition business at Tokyo Electron. Thank you for this opportunity today. Thin film deposition business has been mainly on a batch furnace, thin film deposition equipment, a single-wafer metal deposition system, and PVD for MRAM, which are expected to be adopted in the next generation, and others. This slide indicates the market size of the thin film deposition equipment with a segment breakdown. We are in the space of batch CVD oxidation, batch LP CVD, and ALD equipment, and single-wafer thermal CVD segments, and we have enjoyed certain shares in them. However, going forward, by expanding the product lineup, we should have major growth opportunities in the segments where we don't have shares, not only in the segments where we have share. Now, I believe that there is an opportunity for growth in the sum. Now, I would like to explain the new products that we launched recently to expand the served available market in the deposition market, which has a high growth potential as well as a direction of the future development. First, let me explain the single-wafer deposition equipment. This video compares characteristics between our existing products and three new products featured in the press release at Semicon West in 2024. So please enjoy. Like to know with the model called Trias e+ on the left side of the slide, we have been responding to the needs of customers, mainly for metal film deposition application in critical applications such as upper and lower electrodes of DRAM capacitors. We have been winning PORs from major memory customers. However, in this platform, we can only equip up to four process modules maximum, so customers were demanding further productivity gain. On top of that, because the processes are becoming more sophisticated, the demand for sequential processes where wafer stride multiple processes is rising. As such, there is a need for a new platform which enables a high vacuum when wafer is transferred between process modules. Episode 1 can carry up to eight process modules, and because of the benefits of a high vacuum wafer transportation system, it is a leading edge cluster tool balancing critical sequential processes and high productivity. Episode 2 has seen customer introduction already, where one process module carries two independently controlled reactors called DMR or dual matched reactor. We are also developing a model in which one process module accommodates four reactors and which uses newly developed plasma source called QMR or quad matched reactor. Next, I would like to talk about key applications for Episode 1. This slide talks about the contact formation and processing advanced logic. Currently, it must produce the latest processor node that has more than 10 trillion transistor counts per 300 millimeter wafer, and the same count is needed for gate contact formation. It is a vital process for making devices more high-speed and lower power consumption. Realize lower power consumption. We have been responding to the application with existing Trias e+ platform, but switch over to Episode 1, which can carry up to eight process modules and enjoy a benefit of further reducing contact resistance due to high vacuum is happening. The market size for this process is expected to expand as it is not only used for the contact on the front side of the wafer, but also with the adoption of the backside PDN. Next, I will introduce the inner spacer application for advanced logic as well. As a shift is happening from the existing FinFET structure to GAA or gate all around and next CFET structures, the importance of a gap fill process for extremely fine structure and the difficulty is rising. With the conventional approach using the ALD technology called conformal processor method, homogeneous film is formed against a structure which could lead to closure or seam, which can cause a leak path. A newly developed gap fill process is unique, leveraging a plasma, and it has a characteristic called a capillary phenomenon where quick thin film deposition happens in a narrow space, which enables the film thickness control on the embedded side and the side walls. Furthermore, by fine-tuning with a plasma source that is newly developed, which has a different use than thin film deposition, naturally uniform film modification is possible against the embedded film. This slide compares the performance of existing Trias e+ and the new product, namely Episode 2 DMR. The number of reactors per unit increased 50% from four to six. The device footprint area has been reduced by approximately 35%, and the per unit area productivity more than doubled. With a highly evolved controller, big data can be analyzed after it is collected from numerous sensors embedded in the system, and feedback can be given to processes and maintenance. Also, the energy efficiency has improved, and by continuing to make efforts, we would like to realize net zero in the future. Next, I would like to introduce a PVD equipment, which is a growth driver for a thin film deposition business. We launched a product called EXIM in 2014, and it has been introduced to almost all the customers who develop next-generation memory called MRAM. After 10 years since the launch of EXIM, we developed a new product called Nexia EX, which is not just for MRAM, but with a better space and energy saving. The PVD carries two cassettes per process module and with oblique angles, sputter PVD, and wafer rotation system combined high deposition rate and excellent thickness uniformity are realized. On the other hand, MPVD can carry up to four cassettes per process module, and by targeting multiple materials, it has a capability of tuning film composition that is complicated. Nexia EX is targeting replacement demand for EXIM, which is an existing model for MRAM, and because of its excellent film tuning capability, we are exploring the application to metal hard mask process, and we may be able to make proposals leveraging a portfolio such as conductor etching equipment for processes as well as gas chemical etching equipment for detaching films. On top of them, capitalizing on high productivity, we are obtaining PORs for thick film monolayer application called overburden. There was a press release about this at SEMICON last year. Finally, let me touch on initiatives for batch thermal processing deposition segment. This segment has the longest history among semiconductor production equipment businesses, but products are evolving day by day, and as a result of incessant innovation, they are changing all the time on top of the long-standing new LP CVD and other processes by leveraging high productivity of a batch method, processes are expanding in the ALD process. By leveraging our strengths that we have both a batch device and a single-wafer thin film deposition equipment, so far metal thin film deposition was mainstay for single-wafer deposition system, but now insulation film application is under development, especially in applications where device structure aspect ratio is extremely high, such as 3D NAND. Batch system has advantages such as a high flow rate of process gases and longer processing time than the single-wafer method, and each time about 100 wafers can be processed. So we should be able to make a major contribution to reducing COO on the part of our customers. We will continue to actively work on the evolution of the equipment performance for this segment going forward. So far, I have quickly outlined initiatives of our thin film deposition equipment business. In the next growth scenario of Tokyo Electron, it is vital that we raise a position in the thin film deposition market, and to this end, we are currently launching a number of new products to strengthen our engagement with our customers while powerfully promoting collaboration. Thank you for your kind attention. Next speaker is from Diverse Systems and Solutions Business Unit. The general manager, Mr. Kaneshiro, will talk about the proposal of equipment to satisfy the various needs. Good afternoon. I am Kaneshiro, DSSBU Diverse Systems and Solutions Business Unit. First of all, let me present an Acrevia that we released last July. In promoting semiconductor scaling, which becomes increasingly difficult, the critical challenge facing the customers is how to make the best use of the very expensive EUV lithography system. Acrevia is a system to process line growth and correct pattern profile in the auto fine patterning process with EUV lithography. By radiating gas cluster beam developed by our company to the substrate, Acrevia can significantly improve productivity and reduce the cost of the EUV patterning process. Let me show you the video now. Thank you. Let me describe the technology in more detail. As shown in this diagram, due to the limitation of resolution lithography system, a certain pitch should be maintained between two pattern features. Therefore, in order to form auto fine pattern feature, it is necessary to conduct multiple exposures. However, when Acrevia is used, firstly, pattern feature with adequate pitch are formed with EUV lithography system, and then Acrevia etches the pattern features laterally to form auto fine features with single exposure process. Without Acrevia, one wafer is processed with two EUV lithography systems, but with Acrevia on the bottom, two wafers can be processed with two EUV lithography systems. Acrevia, therefore, drastically improves the productivity of EUV lithography process. Acrevia is low damage gas cluster beam system that Tokyo Electron developed with its own proprietary technology. Acrevia can freely adjust beam incidence angle, and it features unique wafer scanning technology called location-specific processing. These functions can enable Acrevia to freely adjust within wafer etching distribution in X, Y, and Z directions. In addition, Acrevia can remove defects between featured patterns and also correct line edge roughness, line width roughness to contribute to yield enhancement. Acrevia is developed and manufactured by Tokyo Electron Manufacturing Engineering of America, TMEA, located in Minnesota and Massachusetts. TMEA also provides low damage physical cleaning system, which can be applied to HBM and advanced packaging. Tokyo Electron acquired this American group company in the past. TMEA, blessed with very unique creativity and advanced technological capability, will release one and only equipment one after another. Next, I will talk about the MAGIC market. Magic stands for metaverse, autonomous mobility, green energy, IoT, and information and communication. So we call it MAGIC market. In the field of metaverse, semiconductor production equipment is essential for micro display and optical waveguide. Autonomous mobility means autonomous driving. Driverless taxis, which are already in commercial use in the United States, are equipped with various semiconductor sensors. In the field of green energy, high-efficiency power devices are essential for electrification of cars and low-power consumption servers. The MAGIC market is defined to embrace broadly diversified semiconductor device market segment, as well as advanced logic memory market. WFE sales in the MAGIC market are expected to be doubled in 10 years to come. By leveraging our advantage based on broad product portfolio, we are aiming at emerging applications with high growth potential and developing and delivering production equipment designed to fit devices for these applications so that we can provide solutions for device development stage as well as manufacturing stage. Also in TMEA in the United States, we plan to start up demonstration lines for the MAGIC market in April 2025. At present, advanced devices keep evolving through device scaling, multi-layer stacking, and heterogeneous integration. In the leading-edge domain, technology development is advancing upwardly in this diagram. In parallel, as in the MAGIC market, devices get increasingly diversified. Semiconductor market expands laterally as well. Materials for these diversified devices are also diversified. In addition to silicon, various materials such as silicon carbide, GaN, LT, and LN are adopted for specific applications. Also, glass is used. Wafers of different diameters, such as 300 millimeter, but also 200 millimeter and below, are used, while such substrate as panel-level package for future AI server application is rectangular in shape. In addition, we will support our install base, which grows by 5,000 units every year, both in leading-edge and MAGIC fields, to maximize technology innovation and productivity in the customer fabs. And we try to support customers to maximize technology innovation and productivity in customer fabs. The install base grows steadily every year. We are working to expand our service business. Thank you very much. This concludes my presentation. I talked about new product Acrevia and MAGIC market that the DSS BU's unit is addressing. Really appreciate your continued support. Next, I'd like to invite Mr. Akiyama, Division Officer, to talk about the technology trends and business opportunities in assembly processes. Hello everyone. I am Akiyama, in charge of back-end process. Today, I'd like to explain technology trends and business opportunities in assembly process. This slide talks about the trends of transistor counts per package in advanced logic device. The vertical line is a transistor count, and the horizontal is the year. Semiconductors have been increasing transistor counts by clustering of the device according to Moore's law, which is a rule of thumb. What's notable these days is that devices for HPC or AI have been driving the growth of the transistor counts dramatically. In HPC and AI devices, together with Moore's law, what's enabling this is the advanced package technology, which can implement multiple chips to 2D and 3D directions. Especially, the introduction of a direct semiconductor bonding technology is accelerating in front-end processing and advanced packaging processing to boost the device performance. Today, I would like to introduce the initiatives of back-end process around 3D integration using this bonding technology. The bonding technology we are currently focusing on is not using existing wire bonds or bumps, but connects semiconductors face to face and is called a fusion or Cu-Cu hybrid bonding. Bonded electrode area can be scaled so application area becomes wide and not just a wafer to wafer, but also die to wafer is targeted for this development. This is a typical process of this bonding technology. As you can see, this is a process integrating a plasma control and a clean technology, which are process technologies together with mechanical alignment technology. These are technologies owned by our company alone, and while incorporating advanced technologies and know-how, efficient equipment or product development is enabled. This is our strength. Currently, for both the front-end process and advanced packaging 3D integration, leveraging this bonding process is making progress, and our engagement with customers is accelerating. This slide shows the business opportunities for our department in the production of HPC and AI devices. On the left is a front-end process, and we expect that this bonding technology will be adopted for all advanced devices. To be specific, for backside PDN, which is a backside wiring structure, and CFET, for which development is underway as next-generation transistor, and DRAM, which is used for HBM process development for this bonding technology, is ongoing. On the right is advanced package process, implementation technology, and testing technology are business opportunities for us. Implementing technology is currently seeing development and introduction of various methods and technologies. Currently, in stacked memory represented by 3D IC and HBM, the process development using this bonding technology is making progress. Also, after the implementation to boost yield, it is important to realize 100% good quality for KGD, which is an individual chip, to ensure at wafer and chip level, testing under the same environment as the environment in which devices are used would be necessary. What's needed here is a thermal technology, which can precisely control heat generation during a test. In our company, we have developed thermal technologies over many years, and product development for the testing and using advanced packaging is making steady progress. As such, business opportunities in HPC and AI devices are widely spreading for both front-end processing and advanced packaging process in device production at the same time. First, I would like to introduce the initiatives in the front-end processing. This slide summarizes the devices to which the bonding technology is applied and their trends. In front-end processing, not only advanced logic and DRAM mentioned in the HPC and AI devices, but also including CIS and NAND, all key devices are seeing the introduction of the bonding technology. Also, in terms of the number of bonding, it is moving from a single to multi-bonding, and this market is expected to grow going forward. For example, in CIS, already a mass production is taking place with two-time bonding process, and in NAND, to increase capacity and performance, a roadmap to multi-bonding has been created. Our company is focusing on resolving the technical challenges, and we are making steady progress in acquiring PORs from customers. Next, I would like to introduce initiatives in advanced packaging. This slide explains a typical case of application of this bonding technology to advanced packaging. On the left-hand side, there is stack memory represented by HBM, which continues to mark significant growth. Currently, the mainstay is HBM third generation using a micro-bump connection, but for further stacking and boosting of heat release, the introduction of a copper hybrid connection is a strong candidate for the next generation HBM production. On the right is 3D IC. There are typical cases such as 3D stack IC, where a single SoC is split by function block, and heat spreader where better thermal conductivity materials are directly bonded. Especially in 3D stack IC, each functional block can be produced in a more suited wafer process, which not only boosts performance but also reduces the costs of further expansion of the application, is expected. I just explained the stacked memory and 3D IC, and for each, depending on the wafer yield and die size, wafer-to-wafer and die-to-wafer bonding processes are under development. We are accelerating the development of high-value equipment and processes at the same time. This is our timeline estimation for bonding process equipment I've introduced today. The front-end process is blue, and the advanced packaging is green. Including all equipment related to this process, CAGR from calendar year 2025 to calendar year 2030 is expected to be very high at 24%. The application of this technology is set to expand going forward, so we are developing products to make it a new pillar of our mid- to long-term business. The bonding process explained today represents a significant technological inflection point in next-generation front-end process and advanced packaging requiring further technological innovation. Tokyo Electron owns the strengths of having all the necessary technologies for realizing this innovation in one company, enabling us to respond quickly to customer expectations. Engagement with key customers is ongoing, and through our next door strategy, which involves establishing technology centers close to our customer sites, we are working to accelerate the evaluation cycle with actual devices while preparing for steep ramp in mass production. Thank you for your kind attention. The last speaker is from ATS Business Unit. Mr. Sato will talk about product strategy and assembly process. Good afternoon. I am Sato of ATS Business Unit. I'll talk about product strategy in assembly process. One of the critical technologies for next-generation device manufacturing is fusion bonding and copper hybrid bonding in assembly technology. The fusion bonding and copper hybrid bonding are used also in front-end process to produce devices, and they are also adapted in advanced packaging process, which integrates multiple chips in one package. Today, I'll present our product strategy focusing on these technologies. This slide shows our 14-year history of launching assembly and test systems. From the left, in 2011 and 2012, we launched bonding-related systems, which are our first product for assembly process. They are Synapse family. Synapse S for fusion bonder, for permanent wafer-to-wafer bonding, and V and Z are bonder and debonder for temporary bonding. In particular, Synapse V and Z family is used in the manufacturing process of HBM, mainly with stacked DRAM for AI devices, along with the growth of AI applications such as ChatGPT. Sales of this family have been growing rapidly since 2023. On the right, many of these products are related to fusion bonding and copper hybrid bonding process. This bonding technology is increasingly adopted in front-end process and advanced packaging process. We are launching this product to meet market needs. Recently, we released a high-precision version of Synapse S wafer bonder, Ulucus L, which is wafer edge trimmer, and Ulucus LX, which is extreme laser lift-off of wafer. Also, for advanced packaging to integrate multiple chips, we are proceeding with product development. To enhance the yield of advanced packaging, it's important that each chip is 100% good. The key is how to control heat dissipation during the test process. We applied heat absorption technology that we have fostered for years to our latest product, Praxa, which is under evaluation by the customers. We will further expand our product portfolio for advanced packaging, such as die tester and generation assembly system. Really appreciate your future expectation. This slide shows the front-end wafer bonding process and our product portfolio. Let me describe how our products are used in front-end process. The front-end bonding process is composed of two steps, essentially. In the first step, two wafers are bonded together, and the second step, unnecessary silicon wafer is removed. Synapse S performs the wafer bonding. In the second step, when silicon wafer is needed in the post-bonding wafer process, we propose a laser trimming system, Ulucus L. When silicon wafer is not needed in the post-bonding process, in such a case, Ulucus LX is effective as it adopts extreme laser lift-off technology to remove silicon wherever necessary. For this extreme laser lift-off, we are developing technology to reuse removed wafer, as you can see here. There is our proposal for bonding process. I'll present some of the products. Firstly, I will present wafer-to-wafer permanent bonder Synapse S. This system incorporates technologies derived from the front-end process. For example, our plasma technology is adopted in pretreatment of bonding, and by using a highly reliable clean platform, we are also able to accomplish efficient product development. Though we had no experience in introducing bonding technology to the front-end process, since the product launch in 2017, we have been overcoming various technological challenges through company-wide effort. This becomes our strength. At present, we are working with major customers in evaluation of these bonders towards their introduction into advanced memory and logic mass production line. For next-node device production, we share a roadmap with our customers and engage in preparation towards mass production. This shows wafer bonder technology roadmap and relevant challenges. For logic, shown on the top, patterned device substrate and supporting substrate are bonded together. It is required to minimize errors induced by distortion caused during the bonding process. As shown in the right-hand side, since distortion factors are different in center, middle, and edge of wafer, we have developed optimum hardware and process for each location. For NAND, along with the increase of layers and capacity, wafer warpage is worsened. In the future, multi-layer bonding. It will become necessary to bond warped wafers together. The NAND-specific bonding challenge is how to correct and optimize wafer warpage to achieve sufficient bonding accuracy. As shown on the lower-left diagram, there is a correlation between wafer warpage and errors. We have repeatedly improved hardware and bonding process to raise bonding accuracy of warped wafers. For DRAM, the bonding technology development will be further accelerated in the future by leveraging our leading-edge hardware technology and process know-how, where we will address customers' requirements in a timely manner. This slide shows laser technologies, Ulucus LX, the post-bonding process. As shown on the left, we released this new product last December. The post-bonding process is to remove unnecessary silicon after wafers are bonded. We developed XLO, extreme laser lift-off technology, and applied this technology to Ulucus LX. As shown on the right, with XLO technology applied, unnecessary silicon wafer can be removed from the thin film device layer by using laser. Compared with the conventional technology, XLO technology can improve not only process performance but also environmental performance. Next, I'd like to describe the value of this technology. On the top, two process flows are compared with each other. The gray portion shows process flow using conventional technologies such as grinder and blade edge trimming. The blue portion shows XLO process flow using laser technology. As shown here, by using XLO, number of process steps can be reduced significantly and removed wafer can be reused. On the bottom, you can see the value offered by Ulucus LX using XLO technology. From the left, as wafer edge is not trimmed, effective silicon area is increased by 1% or more. As I said before, in process flow, the number of process steps can be reduced. As for environmental performance, since silicon is not ground, DI water consumption is reduced significantly by 90%, and silicon sludge is not generated. When wafer is reused, CO2 emissions can be reduced as well. Ulucus LX features both outstanding process performance and environmental performance. Now, I'd like to show the video of Ulucus LX. Please enjoy. Thank you very much. Finally, I will summarize the message in today's presentation. Along with the arrival of 3D integration era, we are accelerating the development of equipment for bonding process. We will proactively develop bonding technologies essential for next-generation device structure leading the industry. We will further enhance ongoing engagement with major memory and logic customers so that we can expand applications of bonding technology and realize its introduction to the mass production line. Thank you very much for your kind attention. We'll have questions and answer session until 6:00 P.M. Japan time. We can ask questions either in Japanese or in English. But as our speakers are on the Japanese channel, please allow us to take audio questions only in Japanese. If you ask a question in Japanese, please click the raise hand button on the Zoom. For details, please refer to the instructions attached to the invitation email. I will call the name of the person who asked a question one by one. Our secretariat will contact you in advance, so please check the Zoom chat box as we will post the audio contents of this meeting on our website in a couple of days. Before asking a question, you are kindly requested to identify yourself by name and affiliation and speak slowly and briefly. For questions in English, please use the Zoom chat box to give your affiliation, name, and question in text and send it to our secretariat. We will refrain from answering questions if your name and affiliations are not given. On the Japanese channel, we will translate your English question and we will read it out in Japanese, and speakers will answer in Japanese. On the English channel, question and answer will be simultaneously interpreted into English on a real-time basis. As we'd like to take questions from as many participants as possible within the limited time, we'd like to take one question per person. Questions in English will be received in text. So if time allows, we will take additional questions. Since today's meeting is intended to present our mid and long-term growth potential, you are kindly requested to refrain from asking questions about current situation. Now, let's take a first question. CLSA, Yu Yoshida-san. Please go ahead. Thank you very much. I am Yu Yoshida of CLSA. Thank you. So I'm allowed to ask just one question about the mid-term management plan and what you have explained today. I have a question covering both aspects. So in the final year of the mid-term management plan is a year after, so there are new regulations against China being discussed and so on. So you explained some products. And which products will be making more contributions, and how can you reach a JPY 3 trillion sales target? And for each of your key products, if you have any idea about how much contribution each of them will make, please share that with us. And also, operating profit is 30.5% was the third quarter, and in March of 2027, it will be 35%. So with the digital transformation and so on, factors other than sales expansion, how much can you raise the profit? So in relation to the mid-term management plan and explanations today, if you could comment on these aspects, please. So Mr. Kawai, the President, will respond to the overall aspects. Well, thank you very much for your question. So this is about the overall situation. So let me respond to this question about net sales, which should be JPY 3 trillion, and then 35% or more is operating profit and 30% ROE are mid-term management targets. And as far as this fiscal year is concerned, JPY 2.4 trillion approximately is the net sales we should be able to achieve. And in fiscal 2027, double-digit growth is what we are currently aiming at or discussing. And from such a perspective, these net sales are over JPY 3 trillion given the current POR acquisition status and the launch of new products making good progress. Considering all these points and WFE trends, we believe that this top line is achievable. This is my strong feeling. And basically, the products added value and the services added value are the areas where, by introducing high-priced products, we can improve the gross profit margin. We have been improving the gross profit margin. And currently, 47% is a gross profit. And with the increase of top line and gross profit margin with these dual engines, if you like, we'd like to reach 35%. So this year is 28%. I mean, this fiscal year, that is our expectation. And with these dual engines, we'd like to reach 35%. So where do we grow? In the past, I mentioned this on, and also one of the presentations, I mentioned this. There is a blue and green part. So overall, we will be growing, but the largest market will be the etching market. For sure, this market will make a major contribution. And going forward, in regards to the risks, there are various macroeconomic trends. And on a daily basis, there are things that are seeing growth potential. So growth investment and development investment in these areas will not slow down. Having said that, this is a challenging target, but because this is a challenging target, it means a lot if we can achieve it. So that is why we'd like to keep making efforts to ascend as a major player. We are seeing a very steady, good progress. Thank you. That's all for my explanation. Thank you very much. Thank you very much. That was very helpful. That's all for my question. Thank you. Thank you very much, Mr. Yoshida. Next question is from Mr. Wadaki from Morgan Stanley MUFG Research. Thank you very much. This is Wadaki from Morgan Stanley. Thank you very much. I learned a lot from your presentation. Thank you very much for a very clear explanation. One question. So I want to ask about the mid-term management plan and targets. You are now making profit on a steady basis. So the profit is accumulated. So 1 trillion JPY operating profit can be achieved in two years to come. So if you have maybe 30% of ROE, it might be difficult because of the higher profit. You have been aggressive in the shareholder return policy. But I think when you think about the continuation of the shareholder return policy, and I'm going to do some aggressive targets. So Kawamoto-san, what's your answer to this question? Kawamoto-san, please. Thank you very much for your question. What you said, it is true. The profit is expected to be higher by having a higher profit margin, 3 trillion JPY, 35%. If we can achieve them, then 1 trillion JPY of operating income can be achievable. That's what you said is correct. So when we have the ROE, it might be affected because of the high capital on our side. But as you know, in this fiscal year, we conducted the share buyback two times this fiscal year. So there are various factors considered and implemented to share buyback. And we are going to conduct the share buyback flexibly in the future. So we need to conduct appropriate shareholder return policy properly so that we can achieve more than 30% ROE in the future. T Thank you very much. Thank you very much. Well, thank you very much, Mr. Wadaki, for your question. The next question is about Goldman Sachs and Mr. Nakamura. Please go ahead. Well, thank you very much for your detailed explanations today. In regards to the call to develop a business, there is page 22 of the slide. On the left-hand side, what you are showing is the ultimate way to develop technology. On the right-hand side, there is a DRAM research product. On the left-hand side, you see the specs. All of your specs are better than your competition. So there are no demerits or weaknesses, it seems. But if you make a comparison between yourself and peers or competition, if there are any inferior aspects, could you please share them with us? And some competitors for DRAM makers are getting PORs and so on. They have made some announcements. And now, key customers are making assessment or evaluation for your technology. And in your new platform, you will be able to get PORs. And could you please talk about the timeline? Now, Yasuhiro-san, please. Thank you very much for your question. So let me respond to the question. Yes. What we are currently developing, ultimate way to develop technology, looking at all the performance values, we are better than our competition. We have a prospect that we will be far better than the competition. So the conventional way to develop technology, this ultimate way to develop technology is an extension of the conventional technology. So this is very lithography-friendly. So customers are expressing high hopes. And as I explained earlier, towards mass production, evaluation is underway. On top of that, from which generation will this be applied? Well, already, our way to develop technology, D1B generation. Some customers of that generation are using this for mass production already. And D1C and after MOR processes, some of them may see some competition with us. And earlier, I already explained this. So if I could repeat myself in terms of performance, the performance is spectacular. It's very high. So in this way to develop technology, high reliability will be a major contribution area. So amongst the customers, DRAM, 3D IC, and logic and then, and after, they will be using this technology. Thank you. Thank you very much. Thank you very much, Mr. Nakamura, for your question. Next question is from Shimamoto-san from Okasan Securities. Shimamoto-san, please. Thank you very much. I am Shimamoto from Okasan Securities. I have a question regarding bonding process. So, page 101, the market size compared with your sales condition, the share should be about 20% plus. I think that's your share. Is that correct understanding? And front-end process and advanced packaging, you divide into two classifications. And your product portfolio, which you take advantageous position, front-end or advanced packaging? Sato-san, could you answer to that question. Thank you very much for your question. This is Sato. So as for market share, in our company, the bonding market doesn't show any statistical data yet. However, according to our focus or estimation against the time, our market share is more than 20% according to our calculation based on our calculated time. Quite recently, we met up with the research companies, so the figure will become clear. I think our share is more than 20% according to our calculation. As for your next question, the front-end or back-end advanced packaging, in other words, which one is better for us in terms of the product introduction of our company? As of today, the front-end process is our focus area. Our focus area is front-end. In particular, we don't take one out of two, but so hybrid bonding or fusion bonding, when those technologies were established in the past, we set up the targets and try to come up with the most effective path for the growth. That is the leading edge, logic and memory, front-end bonding. That's the area we tried to focus. So as of today, we are focusing on front-end process. For the back-end process, advanced packaging, we need to take some more time, so maybe five years or ten years to come. We can have die level or advanced package area application will be expanding furthermore. So we should look at the growth and technology innovation. We would like to grow our business furthermore. Thank you very much. I have one follow-up question. For back-end area, when you penetrate into the back-end, what is the gross profit margin? Is it possible for you to maintain the gross profit margin? I think the price could be different for the back-end from the price for the front-end process. Thank you very much for your question. Today, as I said in my presentation, so semiconductor evolution is the important thing. Not only front-end process, advanced packaging will be driving the semiconductor market. Technology-wise, semiconductor performance is accelerated. We have those technologies. That's our focus area. In that segment, our customers are interested in device performance enhancement and high value added can be provided by our products. Therefore, we are now in the market, and we do have the product portfolio. As for the profit, I think we have the same level of profit for the advanced packaging. Thank you very much. Thank you very much, Mr. Shimamoto, for your question. The next question is Mr. Yasui of UBS Securities. Yasui of UBS Securities, thank you. Cryogenic etching, I have a question about that. So this time around, you are using this. So I think this is very important, and your competitor is now introducing new products. Etch rate is rather high. Then customers may be interested in and adopt high etch rate product of your company. However, from an outside third party, where can you differentiate a product from your competitors? What is the competitive area? I think that is a kind of all project. So now you try to reduce the incident angle and the number of electrons induced, and you have the voltage applied to improve the etch rate. So maybe could you let me know what sort of competitive area are you working in? And could you let us know your experience of R&D activities for this topic? Mr. Nishihara, could you answer to your question? Thank you very much for your question, so first of all, about the rectangular RF I talked about in my presentation today. Rectangular wave with high power turned on and turned off. The repetition has some value. As I said in the beginning, that is etching mechanism. As I said in my presentation, each etch chamber, the gas is dissociated, and it's so difficult to apply the gas properly to the area you want to etch. But after etching, we have the byproducts. After etching, you need to remove the byproduct effectively. That's really important. That is the very basic etching mechanism, and the efficient etchant introduction and removal of the byproducts on top of that, and as you said, so vertical energy application, those two things to be applied to each other. So each has its own parameter, and we need to think of an optimum combination of different parameters. That is the key of the technology development. HAR technology, the rectangular wave, the pulse-based turn-on and turn-off. This is how we create the shape of the rectangular wave. We can take the interval for turn-on and turn-off. We can change the power of turn-on or turn-off together as parameters, and on-off timing can be combined in a different way. So there are various ways. There are infinite numbers of combinations of technology factors, and we need to align them optimally to fit the customer's device, which is very critical. Therefore, customer device changes and structure of device changes. So we need to customize hardware to meet customer's device structure, which is very critical in this business. And our competitors are doing the same. So they use various gas chemistries to satisfy the current customer needs by improving the profile of etched pattern. Thank you very much for your interesting answer. Thank you very much. Thank you very much, Mr. Yasui. The next question is from Tokai Tokyo Intelligence Lab, Mr. Kamizaki. Please go ahead. Tokai Tokyo Intelligence Laboratory, Kamizaki is speaking. I have one question. So about the film deposition, I'd like to ask a question. On page 74, plasma CVD and PVD are mentioned, and you believe that the sum will be expanding, especially for the PVD, QMR, a new product that will be launched and so on. So if you can get POR for mass production, maybe performance can be strongly enhanced. How do you assess the potential? And about competition or comparing yourself with others, do you have any comments? Thank you. Well, thank you very much for your question. In regard to the expansion of CVD, as I indicated today, so plasma CVD and PVD are the areas where we don't enjoy a good position, but the markets are quite large. So as we introduced today, using the new products, we'd like to expand our shares in these markets. And that's our strategy. So mainly, in regard to plasma CVD, today I talked about two processes, and both of them are under plasma CVD. And mainly, advanced logic requires very low temperature. And what we can offer today as an application is quite numerous. It is expanding. So front-end contact and spacer are not the only applications. Today, I couldn't talk about this because of the time constraints, but next generation interconnect materials after copper, metal gap fill, and air gap provide innovative technology that can reduce parasitic capacitance. This will be realized in the chamber to be embedded into the platform that I discussed today. So it will still take some time before they start making contributions to the business performance, but towards 2030, we would like to make good preparations. Thank you very much. That was very clear. Kamisaki-san, thank you very much for your question. Next question is fro m Yamamoto-san from Mizuho Securities. This is Yamamoto from Mizuho Securities. Thank you very much. So Nishihara-san, I have a question regarding etcher, Nishihara-san. So you want to become number one in etch systems and really expect high, but I have been expecting your company for over 20 years, but against Lam etcher, what is the disadvantage? The TEL etcher, so conductor etcher, that's the weak point. Or you talked about HAR or PHastIE before and after. TEL is developing something good all the time. So you are providing wonderful products all the time. But when you look at Lam, your competitor, compared with Lam, what is your disadvantage? And what is the reason why you are not able to catch up with Lam in terms of market share? Thank you very much for your question. For one thing, the customer's needs. We need to satisfy customer needs on a timely basis. So when the customer needs change, we must understand and address customer needs to provide customers with the timely answer. That is really important. So in the past, for etching system, it's only oxide etching, but conductor etching. So there are now quite a few numbers for etch. So how we can satisfy customer needs? Honestly speaking, we were not able to capture opportunities effectively. However, having said that, the technology is evolving, as I said today, over the past 10 years. We have been promoting R&D investment over the past 10 years. So today, I talk about the direct etching, but dielectric etching and conductor etching. We do have the high competitive edge in our etch system. We are proud of our high competitive etch process for both dielectric and conductor etch. So we can exceed our competitor so that we can win PORs in a good way. I have one question. So Alpha tool is not installed soon enough. That's the feedback from your customers. I think that's what Nishihara-san said right now. So, for example, cryogenic etching. So you are quicker than before. I'm sorry, I'm a layman here, but maybe over the past 10 years, so from the viewpoint of users, so you are not so quick enough to provide users with the Alpha tool. What sort of efforts and what sort of initiative have you taken that you have? I think you introduced Alpha tool or cryogenic etcher soon. So could you share your idea with us, please? Thank you very much. So I really appreciate if you view our company in this way. I'm very glad to hear your comment. So for the leading-edge customers, we are looking ahead, two nodes ahead, or three nodes away when we start development over the past 10 years. So we are very active in proactive development. So rather than one node ahead, we should look at two nodes or three or four nodes ahead. We are engaging with customers at the early stage in a proactive manner. And it's also important to develop technologies in parallel for different generations. So also, we shouldn't miss the timing to install Alpha tool. I think that is a major counteraction that we deliver Alpha tool on the right timing. We are working on shift-left basis to satisfy customer needs in a proactive manner. So that's the effort we are going to make in a continuous manner. Thank you very much. Thank you very much. Mr. Yamamoto, for your question. Next is Mr. Hirakawa of Bank of America Securities. Hirakawa of Bank of America Securities. From my side about the bonding, I have a question. So, bonding, it is a 20% share that you enjoy against the term, and 20% share in gaining a 20% share. Which part of your bonding have a strength? For example, you talked about wafer distortion-related advantage that you offer and so on in comparison to competition. What are your strengths? And we still have some hopes that you can expand the share from 20% even more. What are the key points in expanding your share? Please. Akiyama-san, please go ahead. Well, thank you very much for your question. Yes, you just asked a question about bonding. And in one of today's presentations, as we mentioned, we are working on front-end processes and also advanced packaging processes. We are developing bonding products for both. And there are not too many products that have been completed already, only for a limited number of devices. For example, HBM, temporary bonder, and CIS. Some hybrid bonding for CIS and 3D NAND. Apart from them, what I discussed today, logic and advanced packaging and backside PDN, these are the areas where evaluation is underway at this very moment. Where do we have a strength in developing these products? First and foremost, in front-end processes, we have developed, again, some technologies such as plasma technology, cleaning technology, and equipment that requires a high level of cleanliness and platforms and so on. These are the sort of technologies that we already own. While capitalizing on them, we can deliver more value-added bonding processes. For them, we are developing products. 20+% is what we have as a share today. Going forward, from this point on, we believe we can grow still so much. Thank you. Thank you very much. Thank you very much, Mr. Hirakawa, for your question. Next question is from Masahiro Nakanomyo-san from Jefferies Japan Limited. I am Masahiro Nakanomyo from Jefferies. Thank you very much, so on slide 57, cleaning system is shown over here. I have a question regarding cleaning system. So I think 3D NAND chip target applications Silicon Nitride. On the bottom, you can see some processes. To what extent do you think the possibility of the extension as a market? Yasuhiro-san, could you answer the question? Thank you very much for your question. First of all, Cellesta, to begin with, so there are needs in the field of 3D NAND Silicon Nitride process, the recess process. The removal process is the first application of Cellesta. More than that, as you can see, very narrow space processing or to improve the cleanliness or etching uniformity. I think there are emerging applications when the 3D integration will proceed in the future, also for DRAM. That's our expectation. That's the next step to penetrate into the market. That's where we can contribute to the market. On the bottom, for cleaning, there are various processes for cleaning, diversified processes for cleaning. The standard clean, in general, now has various things like single wafer and wet bench. Each one of them has benefits. When we combine the benefits together, we can just apply them in terms of the productivity and COO in the future. So product itself, so when are you going to release this product to the market? Already, actually, some customers are working together with us to evaluate this system, the product. So sooner, within one or two years to come, I think customers may adopt this product. In that sense, for the long midterm perspective, the share in the cleaning system can be enhanced by this product. So that's the product. [Cellesta] can help you to increase your market share in cleaning segment. Is that correct? So compared with competitor, we need to be ahead of competitor for bevel system or supercritical dry system. As I said earlier in my presentation, high productivity batch process, SPM, vapor. So we are ahead of our competitors to introduce those systems into the market. In reality, so [Cellesta] before [Cellesta], we presented some equipment. In reality, they are being adopted by the customer's mass production line. So in short and midterm perspective, I think that will contribute. And also, as for the [Cellesta], in the future, cleaning processes will be increasing in number. Therefore, I think TAM will become rather high, for example, standard clean or the minute wet etching process. That's where we can drastically expand our market share. So at early stage, we can become number one in the cleaning market. That's our target. Thank you very much. Thank you very much, Mr. Nakanomyo. The next question is from Citigroup, Shibano-san, please. Thank you, Shibano of Citigroup. I have seen a lot of questions about the product. So about the smart production in Miyagi, a new production building, I have a question about it. So there were some slides touching on this. And once again, I believe Miyagi started using automated warehouse to a great degree. So a concept of planning for this, when did you start considering this concept and what is the background up to today? To realize a smart production, what sort of economic benefits or P&L impact are you expecting? Especially, HR has a high affinity with this concept. What about other products? Do you believe the same developments can happen with the factory to boost productivity? Could you please comment on the Miyagi new production building? Perhaps Ishida-san can take this question first. Thank you very much for your question about the new planned production building in Miyagi. As you asked in your question, the automation of the warehouse was the starting point. From that point on, the concept of smart production was something that we had already started considering. This time around, with this new production building, we are trying to realize a smart manufacturing or data integration. Smart production as a whole is what we are envisioning back then. So this is really an ultimate shape or state. So robots and humans will be collaborating with each other in the automatic automated warehouse. We have seen some results in the automated warehouse, as I touched upon in my presentation. Productivity has become four times. And without increasing the number of people working on that system, we were able to realize this productivity gain. So going forward, assembling, production, and inspection, we'll see some introduction of automation. So we will be increasing capacity without increasing workforce. So those are the benefits that we are assuming. So should I take the second part of the question, economics? Perhaps Kawai-san can take that part of the question. Well, thank you very much. Let me respond to that question. The etching market is the sort of a market where we believe that the market potential is very high. The growth potential is very high. As such, in 2030, around that time, I believe that the market size will be significant in case of this etching market, and by introducing this smart building every year, probably more than 10 billion JPY cost reduction will be possible, so as the sales go up, as production goes up, the benefits of scale merit will be greater, so under our current assumption, we talked about the labor productivity as well as the lead time reduction, so after 2030, at least more than 10 billion JPY of cost reduction will be possible. That is the sort of economic benefit we are expecting. Thank you very much, Mr. Shibano, for your question. May I add something more? Well, earlier, Miyagi smart production concept or factory. I believe that how this will unfold going forward, I will follow up on that. Tokyo Electron's product lineup includes a dry deposition, film deposition process. This is similar to etching because low pressure is used. So perhaps the similar concept can be applied here. We would like to standardize this part by consolidating the function of the warehouse. We'd like to make some future movements. But coater and wet cleaning product groups are different from dry groups in terms of the configurations as well as the production method. So apart from new and specialized products, module by module, partner companies are producing using the customer's sites for assembly. So optimization has made a great headway. So at this point in time, within the formation of the current product groups, we are not really thinking of leveraging this smart production factory. But I touched upon digital transformation a little bit. And regarding this initiative, this is universal irrespective of the product groups. Thank you. Thank you very much. Next question is Tetsuya Yoshioka of Nomura Securities. Tetsuya Yoshioka, please. Thank you very much for your presentations. I am Tetsuya of Nomura Securities. I have a question regarding film deposition system. So page 74. So talking about film deposition. So my concern is ALD. Your measure film deposition system, your share is rather low here for ALD. So what is the current status and what sort of challenges do you have? That's one thing. And this time for film deposition, you are introducing new product. In principle, that is single wafer system in principle, but for batch ALD, do you have any plan to introduce new product for batch ALD? So I have a question regarding your approach to ALD. Thank you very much for your question. So our product portfolio, ALD system, is for batch furnace ALD. Because of time limitation, I was not able to touch upon this, but NT333, that is semi-batch system by dividing space, so the applications are limited to some extent at present, as I said earlier. Along with the device scaling, the CVD will be replaced by ALD in the future, or because of productivity, ALD productivity is not high, by adopting batch process, productivity of ALD can be improved furthermore. That's the area for growing. For ALD, for example, so the deep gap fill process, the ALD is used for memory devices, so NT333, as I said earlier, is used to capture the share. What is unique is, so this is ALD, but high temperature film deposition can be conducted by NT333, so compared with single wafer ALD, the low temperature process is necessary, but the high quality film can be produced because of the temperature, high temperature. So that's the differentiation point of NT333. And this is how we can try to improve our share even within ALD segment. Another thing for batch system, the high K is the major area we are selling our product, but silicon for silicon interposer, new applications are coming out. And we try to leverage our strength so that we can get the portion so that we can improve our share within the ALD market segment as much as possible. So we try to be selective in application, and we provide the optimum product for application so that we can improve our market share. Mr. Yoshioka, thank you very much. Thank you very much. It was a very good explanation. Thank you very much for your question. We have only three minutes. And we have questions. Two questions more. To take space, questions. So Mr. David Dai from Bernstein Research. Thank you for your question. Synapse Si was announced in end of 2023, and Ulucus products were announced in the end of 2024. When do we expect to see them in mass production by customers and in which applications? For example, DRAM and NAND and logic first. Sato-san, please. Thank you very much for your question. There are two Ulucus L and LX. Bonding application is being defined, and we have products rolled out. So logic, advanced logic, NAND and advanced 3D NAND and DRAM. We are progressing in terms of engagements with customers. So the first batter is a bonder, if you like. So we'd like to get POR first with a bonder, and in parallel, laser products will be rolled out. As for laser products, each has a trim and XLO, which is a detachment system, depending on the structure of the device of the customer as well as objective. The customer makes a selection, so at this point in time, on the part of the customers, they may start the introduction of bonding mass production, or they may not. So depending on the answer, first, we will work with bonders, and then lasers will follow. We are developing products to that end, and it's difficult for me to answer your question clearly. And the mass production and evaluation timing will coincide with the application timing by the customers, so we are making development to that end. The answer will be in the near future because it will coincide with the timing of the application on the side of our customers. I cannot answer this question, so that's all I can say. Thank you. What I will be able to say if I can disclose that sort of information, but I cannot. So that's my answer. TD Cowen, Krish Sankar asked this question. This is the short-term question. So what is your WFE view for this calendar year 2025? Of this, how much is China WFE? In particular, the U.S. SPE companies have spoken about export restrictions impacting their revenues this year. It seems like you have no issue shipping to China. Is that correct? What are your restrictions in terms of logic, NAND, and DRAM for shipment to China? Kawai-san, please. So this is a kind of geopolitical issue as a company. I'm not in a position to answer such question, but we should closely watch the trends. So we want to watch the trend and situation closely so that we can take appropriate action. As for the proportion of the China market, in this fiscal year, about one year ago, the China sales accounted for about 50% of our total sale. That was the situation one year ago. But in this fiscal year, in the second half of this year, the China proportion is less than 40%. For next fiscal year, it's about middle point of 30% level. Around 35% is the proportion of China for WFE. So 30%-35%, maybe even in the future, I think the 30%-35% is a kind of level with China proportion for a longer period. In the leading edge area, the investment in leading edge area will be increasing. The China proportion, just like last year, is very close to 50% at that time. Actually, the investment by the leading edge customer was rather small. But because of AI-related application, the leading edge customer investment will be increasing. That's one of the reasons why China proportion goes down. And now you can see emerging customers last year. Therefore, rather than new investment, mass production capability should be verified in this year. In that sense, we said 35% this year and next year. So leading edge for 2 nanometer node investment will be starting. And own device AI, PC, and smartphone, the leading edge volume zone will be recovering in the future. Therefore, China proportion will remain around 35%. That's the trend for the future, according to our prospect. Thank you very much, Sankar-san, for your question. So now, because of the chat malfunction, it's not possible for some people to send the question by using chat box. So could you send us an email when you want to ask a question? Because we will pull up the answer on our website. It's time for us to close the IR day. So we'd like to continually improve our IR activities based on your precious feedback. So we'd appreciate your kind cooperation in filling out the questionnaire on the Zoom. Thank you very much for joining us despite your very busy schedule. Thank you very much.