Welcome, everyone, to ASML's 2024 Investor Day. I am Skip Miller, Vice President of Investor Relations at ASML. Thank you to everyone that made the journey over here to our headquarters in Veldhoven. Good morning, good afternoon, good evening for all those joining via our webcast. It's been about six months since we made the leadership transition. The handover went well. The team is happy today to welcome you all and give you an update and discuss our long-term strategy and the market opportunity we see ahead of us. Before we go into the details of the agenda of the day, I'd like to start with a few logistics. First, if you look at the space from a safety perspective, the exits, you go up here, here, and you can see where you can go outside on the different locations. Clear the aisles. Please make sure you don't have stuff in the way should there need to be an exit. Secondly, please put all your phone on silent or airplane mode. The restrooms are located if you go outside here or here, up on the top right, my right, your left. Presentations today will be posted on our website shortly after the event. And the in-person Q&A will have both a combination of questions, obviously, from the audience, but also online. And so we'll be able to take both of those after the presentations are complete. For those that are online, if you look at the, you should see on a screen like you see here, which is basically you type in your question and submit. We'll receive those on our end, and then we will try to take as many as possible during the Q&A session later today. For the agenda, first off, we'll start off with our President and CEO, Christophe Fouquet. He'll talk about the industry and the technology roadmap, as well as ESG. Next, Amit Harchandani. He'll talk, Senior Vice President, sorry, and Head of Corporate Marketing. Some of you may know him. He will talk about the end markets and how this translates into wafer demand, and also some on litho spending. Next, we'll go to Peter Vanoppen, Executive Vice President and Head of Business Line EUV 0.55 NA, or also as High NA he'll give us an update on the EUV products, as well as business opportunities. Next, we'll go to Herman Boom, who is the Executive Vice President and Head of Business Line DUV. He'll provide an update on the DUV products, as well as the business opportunities. We'll then go to a short break. After Herman, we ask you all to please be back at the schedule where you can see we'll start our next presentation with Marco at 3:30 P.M. We will go on the webcast here, so we'll try to keep it, as I said, very close to schedule. So please don't be efficient of coming in and out after the break. After the break, we'll go to Marco Pieters, Executive Vice President and Head of what we call our Business Line Applications. He'll give you an update on the Holistic Lithography solutions and the business opportunity there. And finally, Roger, our President and CFO, sorry, Executive Vice President and CFO, he will give you an update on all this, bring all this together with our business model and our capital allocation strategy. Finally, we'll wrap it all up with closing remarks from both Christophe and Roger, summarizing the day. We'll then go into a Q&A, where we'll have all of our presenters come up here. We'll again be taking questions both for the audience, as well as from the webcast. We'll try to intersperse both those. We'll end the program formally at 5:30 P.M. And then for those that are still here in person, we'll give you an update on what's planned between 5:30 P.M. and 8:00 P.M. tonight, which we'll finish with drinks and dinner and the opportunity to network with a lot of the ASML's management team. Before we begin, I need to remind everyone that comments made by management during this event will include forward-looking statements within the meaning of the federal securities laws. These forward-looking statements involve risks and uncertainties. For a discussion of the risk factors, I encourage you to view the safe harbor statement contained in today's press release and presentations, which were posted on our website at ASML.com. Before we begin, before Christophe comes up, I'd like to do a quick video with a little bit of AI fun embedded in here, bring up the energy level, and it's generated by AI, a lot of fun here, but we'll kick it all off and we'll come back and introduce Christophe. Thank you. What happens behind these walls is an enigma for many. We've been thinking smaller and smaller because your dreams kept getting bigger and bigger. Giant dreams that made our world more mobile, more connected, more fun. And it all started in a shed. In truth, these dreams were built on the dreams of those before us, the giants who changed the world many times with their vision, their discoveries, and their principles. If we've seen further, it's by standing on the shoulders of giants. Today, we can make what seemed impossibly small yesterday. Imagine how big we can dream together tomorrow. So now I'd like to bring up Christophe Fouquet, our President and CEO. Christophe. Thank you very much, Skip. Thank you. Hello everyone. So as you can see, AI has got very, very exciting, but it's still not good enough. So we still have to show up in person here to talk to you today. But we are very happy to do so. And I'd like to thank all of you for joining us here or virtually. It's really a pleasure to have you here. And we are, to be honest, very, very excited to have the opportunity to talk with you for the next few hours about the future, the future of the market, the future of technology, the future of ASML. And the ASML teams have been working very hard in the last few weeks to bring you our latest view. And from where we stand, the future of each one of those things is extremely bright and extremely strong. And we're going to try to share that with you. So we're going to talk about a few things today. The first thing, we're going to talk about the market. We could make it short. We were talking about the EUR 1 trillion market in 2022. We're going to talk about the EUR 1 trillion market today. So you could say, well, it's all of the same. Well, not exactly, because AI has come around. And what you will see when I present is that if the size of the market is the same, the mix of the market is going to be quite different with a much stronger presence of advanced logic and DRAM. And we believe that this is a very good shift for ASML. We will talk a lot about technology. Sorry, but welcome to ASML. But we will talk a lot about technology because this industry needs innovation. For AI to deliver on its promise, we need major, major innovation. We need major step on cost. We need major step on energy consumption. And we believe that our portfolio is going to basically help our customer to deliver on those needs. We'll talk about EUV extendability, the power of High NA. we'll talk about how Holistic Lithography can once again help us help our customer basically to tackle those new challenges. On top of technology, we will also talk about many, many things we are doing to improve our product with our customers. We're going to talk about quality. We're going to talk about flexibility. We're going to talk about time to market, all those things that are still very, very important basically to get what our customer needs. We will, of course, also reconfirm our view for 2030. So a few weeks ago, we had a bit of a, I would say, more, I would say, conservative view for 2025. In many ways, this is related to the change of the market we're going to talk about, this big transformation that AI is driving. But when it looks, when it comes to 2030, we are still very, very bullish. I think you have seen that this morning in the press release. And Roger will give you again the fundamental that explain why we believe that 2030 is still a very, very positive year for us. So this is a lot of topics. I'm going to start with global market trends, the roadmap of the industry in ASML, and a few words on ESG. If we look at the big picture, the semiconductor industry remains very, very strong. We talked about that in 2022. What is new is that AI is going to boost this industry even further. And we see that happening today. There's major investment being done in AI. And the rest of the industry is getting ready basically to also release the different applications to insert AI basically everywhere. As I said before, the industry will require major innovation to address the need to improve cost and energy consumption on AI. And this will require to further boost the industry roadmap. Logic, DRAM, we'll see major transformation in order to be able basically to deliver on those needs. And this will result in a product mix which is more towards DRAM, more towards advanced logic, which once again, very beneficial for our customer and for ASML. Our customer, they will remain at the core of ASML strategy. We believe that lithography will remain at the heart of their innovation. If you need more advanced process, I will explain that lithography today is still the best way to drive costs down and to drive energy consumption down. So lithography remains important. I know some of you have doubts about the weight of lithography moving forward. We'll explain to you today that this weight not only will remain strong, but will continue to grow. The focus on logic, advanced logic on DRAM is going to be a very good opportunity for us. When it comes to product, we will talk about the extendability of EUV. We can scale EUV for many, many, many years. We have been spending years to get EUV to work. You know that. You remember that. Some of you are smiling. Now, the good news is we have it. The technology is getting more mature, and we will be able basically to use this technology for many, many, many years. This will offer our customer a way to really drive costs down, energy consumption down. Holistic Lithography is still key. The scanner today is still the only tool in the fab that can be used to correct process. So not only we produce chips by providing lithography, but we use our scanner to improve all the rest of the process. This will be very, very important as customer shift also towards 3D integration in front end in order to increase transistor density further. Finally, on DUV, Herman is going to explain that this is one of the workhorse of the industry. We continue to improve on all product in productivity, in quality. And this will also allow us basically to address a very large set of needs from our customer. On top of that, as you may have noticed, our installed base is growing. We're talking now about thousands of systems, which means that the opportunity for service, the opportunity for upgrades is growing as well. And that part of the business is more and more important for our customer. And as a result, it is a bigger and bigger part of what we're going to do. I think Roger will explain that very nicely in numbers later on. Finally, ESG, this has been an important topic. We have been working very hard with our partners in the last few years so that this industry, with all its partners, all its peers could basically lead the way, I would say, on ESG. We have made huge progress. We continue to make huge progress. We're working very closely with our customer, with our suppliers in order to make sure that we achieve the commitments we have made to the entire world a few years ago. This is a bit the key talking point. I told you that the customer is at the core of our strategy. You are all aware of how successful SK Hynix has been this year, last year, most probably will be next year because they were one of the first DRAM customers moving into High Bandwidth Memory, one of the first ones to basically sense this AI opportunity. And we are very happy that Dr. Cha, who is the CTO of SK Hynix, so one of the masterminds behind the success of SK Hynix, has agreed to make a short video for you. There will be two parts. In this part, he will talk about partnership, what the relationship with ASML means, and later on, I will bring him back to talk a bit more about technology. [Foreign language] So, one of the best rewards we can get in ASML is when our customer tells us that we have helped them to be successful and that they are counting on us basically to maybe be successful further looking at the next generation of technology. So, this for us, I would say, is as good as it can get. And we're very happy again that Dr. Cha was willing to share all of that with you. Let me go back to the market now. So, this is a slide, in fact, we showed you in 2022. And we showed you this slide to explain to you, as you know already, that if we look forward, any major innovation we will see will be based on semiconductor. This was a story in 2022. That's still true. And semiconductor is going to be used everywhere. But on top of that, AI over time will be added everywhere. And today, most probably, as we talked in the past about semiconductor everywhere, we will be talking about semiconductor and AI everywhere. And this is, of course, the biggest change we have seen in the market in the last two years. This will add huge opportunity on the total GDP. Amit is going to talk about that. But this is also going to basically require the entire market to be connected. About 40% of the semi business will be around AI in 2030. The rest will still be about mainstream semiconductor, the semiconductor basically that will generate the data sensor, for example, in order to feed AI. So AI is built basically on the existing ecosystem. And what we will see moving forward is basically a combination of both AI and mainstream semiconductor really driving this market. As you know, our portfolio has been for many, many years addressing both. If we look at the number, this is about what we see. There's a lot of debate, I know, about the size of the market in 2030. But for discussion today, we take EUR 1 trillion, which is still about the mid-range of many experts. You could decide that there's an upside. We won't even fight you on that. But then you can scale whatever we are going to tell you to whatever market number you have in your mind. But for all discussion we'll look at today, we look about EUR 1 trillion. And like I said before, you will see that if the number doesn't change, the mix itself is going to change quite a bit. Now, the other very important thing about this market, it's also a slide you have seen before, is that it remains a very, very profitable market, EUR 65 billion EBIT in 2023. And 2023 was a bit of a downturn year. So this is a lot of profitability and a lot of money that can be reinvested for innovation. And we continue to see very strong investment from the entire ecosystem to do more, to innovate. About a third of EBIT before R&D is being reinvested to innovate. I think we don't know any other industry that does that. And this means if you look at 2024, more than EUR 50 billion of R&D will be spent to create the next innovation. And this has been true for many, many years. And this is, you know, when we look at this graph, we believe that, well, we don't know exactly what will come in five years from now, in 10 years from now, but this is the guarantee that something else is in the preparation. Now, let me go to our customer, Moore's Law. Many, many discussions about Moore's Law. Everyone likes to take its own version of Moore's Law. This is my favorite one. That's showing basically that the number of transistors continues to double per package. So we don't talk about per chips, we talk per package now every two years. This is still very much true. This has not slowed down. In fact, what's happening is that, of course, this number of transistors is going to provide computing power. What happened in parallel to that with Moore's Law is that customer, our customer has been basically also driving the energy down, right? So they've been driving transistor density up two times every two years, energy down 60% every two years. And this was a good way basically to, for example, drive the roadmap on mobile. So this is still true. Well, if I look at AI, in fact, this is in fact accelerating. What you see happening with AI is that the demand now for computing power is increasing a lot faster. And the slope you're looking at is not 2x every two years, it's a 16x every two years. So it's 8x faster than Moore's Law. This is what people who are working on supercomputer, who are going on training model really want to get. And the problem with that is that energy cannot keep up. Energy as a resource is not decreasing anymore per generation. It's increasing also a factor of five every two years. And those two things, of course, are showing the challenge of AI. There was a reason why Moore's Law was important. It was important because it was putting cost in control and it was putting energy consumption in control. So that control is a bit off. Now I'll take an example to illustrate that. So let's focus first on the number of the computing power. So that you can get, you know, this is a kind of supercomputer you have been seeing in the last few months. So if you want to get more power to compute, you just put more chips together. For a few companies in the ecosystem, this is great news because they are going to sell a lot of CPUs and a lot of GPUs. So getting the power to compute is possible. The first challenge is here. Yes, you need a lot of CPUs, more than 20,000, a lot of GPUs, more than 60,000, a lot of memory. And the cost of these things today is EUR 500 billion, which is okay if you are investing to develop your model. And most of the companies can do that. You have seen it thanks to the ecosystem EBIT. But this is, of course, a bit of a problem on the long term to be able to transfer AI to all devices. So that's problem number one. And problem number two is energy consumption. A supercomputer like that is going to require 60 MW. That computer, you see it is only allowing a customer to train basically a number of parameters. This number of parameters is going up very quickly. The graph you see on the right is a graph I took from Lisa Su. She presented that at ITF back in May. She said, well, if we keep going basically on training more and more parameters, you know, at some point of time, we will need a nuclear power plant in order to feed those supercomputers. That's a bit of a challenge. What does it mean? It means, again, we can get the power, computing power, just put more chips together. Great news for the industry, at least on the short term. Cost will be an issue. Power consumption will be an issue. How did we solve that in the past? We go back to Moore's Law. This is the logic roadmap. This is a slide from imec that have been, I would say, shown many, many times. Still the same. What it says is if we look at advanced logics, there is a path. There is a path basically to create architecture that will be more performance and less with less appetite for energy. So that's possible. A few years ago, customers were working on advanced logic. We're not even sure they will need a 2nm node. They used to tell us, well, why do we need it? What are we going to do with 2nm? Who can afford it? What are the applications that are going to run on that? That's only three, four years ago. There was then a risk that this whole roadmap will slow down because if you don't have the need for it, there's no need to drive it. If you hear the story today around AI with our foundries customer, AI customers are extremely eager to get 2nm chips. And they will be equally extremely eager in the future to get 14 Angstrom chips. Why is that? Because that's the only way to really address cost and power consumption. So what I'm trying to say is that AI will again demand an acceleration of the roadmap. That's something we like in ASML, of course, because this is creating opportunity for also more performance tools in lithography. So that's the story for logic. What's happening with memory with DRAM is also very, very interesting. So you're all aware of High Bandwidth Memory. Why did people suddenly get very eager to buy a lot of High Bandwidth Memory? It's simple. It's because today memory, DRAM, is the bottleneck of AI because the structure of DRAM is such that only 30%-40% of the bits are going to be really used basically for computing. Therefore, we need to change the architecture. HBM is the first step. What we believe will happen moving forward is processing in memory. What does it mean? It means that memory will see more and more logic coming together with the array. And that logic is going to be used to improve performance, to improve speed, and to reduce power consumption. So we also expect a major shift on the DRAM roadmap. I think Amit will come back to that. This is mostly the market that will be the most affected in a positive way by AI. So that means practically that when we look at bit growth, which has always been a driver for ASML, when it comes to logic, when it comes to DRAM, very aggressive growth moving forward. And there again, you see we put a cone. There's a lot of debate depending on your belief of AI. Our belief is that when it comes to logic, especially advanced logic, we will see an acceleration. Same when it comes to DRAM. Now, this brings me to us. So if we go one more step in the food chain, talked a bit about the customer. Now we have to talk about wafer processing. And as you know, wafer processing is a combination of many, many processes. You need lithography, of course. You need etch. You need deposition. You need all kinds of processes. This has been true yesterday. This is still true today. For our customer to drive cost and emission, total emission down, they will also have to optimize this process. So they want to make sure that any chips they produce is going to be at the lowest cost and the lowest possible emission. And then coming Holistic Lithography, if you look at the best way to reduce cost, to reduce emission, there are three things. First, you need to make sure that the yield is the highest possible, right? Every transistor you produce, you want the transistor to work. That is a good way to do that. Second, you need to simplify the process flow as much as possible. Dr. Cha was talking about how EUV is being used for HBM. Using EUV on HBM allows a DRAM customer to skip more than 100 process steps, which is a lot. You know, when the total number of processes for DRAM is about 700-750, so it's a big deal. You gain in cost, of course. You gain in emission and even gain on cycle time, and the last one is to make sure that for every step you're going to take, you try to reduce cost and you try to reduce emission, so that's simple, and that's what basically all our customers are asking us to do. Now, if you look at ASML, this is what we've been doing for many, many years. We had KrF, then we had ArF, then we had immersion, then Low NA EUV, High NA EUV, and one day, most probably, Hyper NA. Why do we do all of that? We do all of that to provide our customer with more good transistors at a lower cost. This is also as simple as that. That's the value of ASML, providing the ability to print a lot more transistors at higher speed, lower cost, and we've been quite successful over time going from one generation of tool to the other. If I look basically at the overall curve, you see that this has been quite a significant trend. Now, you could think this is easy, right, but when it comes to lithography, we have many, many different things we can do to achieve that. Before I go there, if I look at this value, so I told you the key for us is to provide more good transistors at the lowest possible litho cost. If we look at EUV alone, and we're going to talk about that with Peter later on, there's many things we can do to achieve that. First one is High NA. NA will provide 150% more transistors per exposure, 50%, 150%. So it's almost three times basically the number of transistors. Second, for every EUV technology, or High NA, we will be able, through productivity improvement, through efficiency improvement, to lower the cost of the exposure of EUV by 30% by 2030. And here, I say it again, when I say we're going to lower the cost of exposure on EUV by 30%, it doesn't mean that we're going to give 30% more discount to our customer, right? It doesn't mean that we're going to draw our gross margin down. It doesn't mean we're going to drive our contributing margin down. Roger is like, no, no, no, no, no. No, what it means really is that we are going to use the R&D team we have in place to innovate, to innovate on cost, to innovate on all the parameters that allow us to do that, and I will come back to that later on. The good news is we can do that, so that's something, you know, you want to do is one thing, but being able to do it is very important, and the EUV technology today gives us this opportunity, and finally, when it comes to environmental cost, emission, EUV will also be able to cut the emission by 50% by 2030, so here you can look at it two ways. You could look at it from the ESG angle, which is a good way to look at it, but you can also look at it from the cost angle because emission is cost. It's a matter of time where this industry will have to really pay real dollars in order to deal with that. This is what EUV can do. If I broaden a bit this value equation to our entire portfolio, and the team will come back to that, there are many, many, many different axes we can drive in ASML in order to get more transistors at lower cost. I talked about yield. This is going to be my presentation with Holistic Lithography. High NA, Hyper NA, accuracy, which sometimes we call overlay or EPE, Edge Placement Error at ASML, productivity, of course, very, very important. When it comes to cost, reducing the system cost, you know, that's something that we work extremely hard on to make sure that every machine is cheaper. Lifetime, our system, I think Herman is going to talk about it, especially with DUV. We intend every system to last with our customer for more than 20 years. That's also true for EUV, by the way, right? Also, we started to ship those for only five years. We're already working to make sure that they will last for 20 years. It's good for our customer, and it's very good for our service and upgrade business. Operational cost, environmental cost. So we're going to work basically on all those axes in order to drive the value to our customer. Now, let me go back for a second to our customer, and they will introduce a bit now what is needed moving forward. [Foreign language] So, as Dr. Cha said, there's quite some work moving forward, and I'll come back to that, especially it comes to DRAM. But if I look first at the big picture of the industry, so this is the roadmap, pitch dimension for logic. What you see here, yes, shrink has slowed down. I think this has been the case for many, many years, but shrink is still happening, meaning that neither logic customers nor DRAM customers have given up, sorry, on shrinking. They will shrink as long as nothing stops them from doing that. And what it means, if we look at our customer roadmap, the best way to shrink using a simple process is to use more EUV layers. And when it comes to advanced logic, when it comes to DRAM, we still see a significant increase, node and node, year after year, of EUV in both advanced logic and DRAM. So here we look at the 2025, 2030 horizon, so we have a pretty good understanding of what customers are going to do. And if we translate that in spend, and both Amit and Roger will come back to that, you look at 10%-20% for logic and even more, 15%-25% for DRAM. One of the reasons for that is what Dr. Cha was explaining. He told you in the video, well, with EUV, I can still reduce the amount of multi-patterning layer. Why is that? So when it comes to multi-patterning, there's a lot of different patterning schemes, and we picked three on this slide. So these are the blue lines here. And what you see here is the cost of patterning over time. The blue line is multi-patterning. The purple line is EUV. EUV, we know how to take the cost down. It's a lot harder with multi-patterning because immersion tools, Herman will show you, are a bit limited when it comes to productivity because of the water between the lens and the wafer. If we move too fast, we break the meniscus and we get defects. So we're limited physically in how fast we can go with immersion. All the other process tools, etch, deposition, also struggle to get better productivity, better cost. So we see basically a bit of an upward trend for multi-patterning. The cost of EUV is going down. That's one of the reasons why in 2019, EUV was adopted to replace a lot of multi-patterning. But as we continue to go down, we see more opportunity, especially with DRAM, to convert more layers from multi-patterning to single exposure. So this will happen in the next few years. And if you go a bit more into the detail of those use cases, at equal cost, single exposure, multi-patterning, single exposure makes more sense because it's simpler, it's faster, et cetera, et cetera. And what you see here is that for every one of those use cases, we'll be able to shift a large part of the patterning cost from non-litho to litho. This is for us a way to build up more EUV layers, but I will say to build up also a much higher litho intensity. This is something we will continue to see. This is the reason why basically we built EUV in the first place. And High NA. why do have High NA because what's happened with DUV immersion in the past is about to happen again Low NA EUV, meaning that at some point of time, you need to do multi-patterning Low NA, more complex, more expensive, et cetera, et therefore, High NA opportunity is happening now. And this is why Peter will show that we have many, many customers evaluating the technology today in the lab, meaning they come here even before they get a tool because they are impatient to find out much High NA can help. We have a few good first examples why High NA could help. This is logic. Free-mask could become one with about 35% cost reduction. This is quite a bit. This is a situation we will see around what we call 14A or A14 node. What's also important, and that you may not know, that High NA, single exposure, gives back a lot more flexibility to the designer. If you use multi-patterning, the designer can only use vertical and horizontal lines to create their pattern. If you use High NA, you can use whatever you want. You have like a thin brush that allows you to design whatever you want. This is something our customers are going also to start to look at because they see that High NA is working. This is, of course, the next trend. Over time, some of Low NA layers, so whenever we're talking Low NA or 0.33 NA equivalent exposure, so we still look at the exposure Low NA, but some of those exposures will to High NA. and we will see the of High NA layers going up. Around 2030, we believe we'll be somewhere between four and six on average at advanced logic customers, 2-3 on DRAM customers. And of course, as we move forward, those numbers will continue to grow because this is the story repeated itself, as we saw it Low NA. now, the other very important about High NA, the other very good news, is that we have now a new optics technology. You could say, who cares, right? We have already optics technology. But the optic we have developed with Zeiss can be, in the future, also used Low NA and can be also in the future used, sorry, for Hyper NA. And that technology will allow us to reduce the number of mirrors on Low NA tool. Every mirror costs us productivity. If we take out one mirror, we get back 40% light. If we take another one, we get another 40% light. So this new optic allows us to envision a roadmap for EUV, which will boost productivity for many, many years. And we have planned, if we look all the way to the end of the next decade, mostly to take EUV technology towards 500 wph, again, because we can. And this is thanks to the Zeiss optic we have developed. So maybe you missed that part, you know, when we on High NA, but the intention was to get the High NA tool, but also an entire roadmap, basically, that we can use moving forward. So this one is one important part of the roadmap. The other important part is the source. So we have struggled many, many years to get to 200 W. Today, our tool uses about 500 W. We have demonstrated 700 W, and we know how to go beyond one kilowatt. We have a good idea now to do that. There's a short video here, so we always like to brag a bit about our EUV technology in ASML, but I wanted to show you that, just to show you again the uniqueness of the technology. So what you see here is the tin droplet. So you remember we hit 60,000 of those droplets every second, right? So this movie itself is a fraction of a second, right? It's one second divided by 60,000. And what you see happening here, so you see the droplet that is being hit, not once, not twice, but it's being hit three times by a laser. So the first two times is to make it as large and gaseous as possible. The third time, basically, is to get the power out. This is years of work. And this is why, when it comes to EUV, we feel pretty good also that it will be quite some work for anyone to be able to repeat this technology. So there's one engineer in the room. That's very, very important. And I think this is a bit of a visual of why we are also so bullish on the EUV roadmap. Now, if I translate that into the roadmap, I simplify it a bit. So this is what you Low NA, High NA, two platforms, two different optics, one source. Moving forward, we will be able to increase the system commonality from 50% today, which is already pretty good, by the way, to more than 90%. And the reason for that is that we'll be using pretty much a platform that is very similar for all tools. We'll use the exact same source, and the idea is that the only thing that we have to change is the optic. So that will be used Low NA, that will be for High NA, and if we need it one day, also for Hyper NA. And if we need it one day is also very important because I will show you later on, most of the time for Hyper NA will come. We're still debating when, 2032, 2033, 2035. It depends a lot on our customer. But when it comes, if we had to develop a platform from scratch, this would be too expensive. If we have the platform and we just have to put the new optic, then we have the flexibility to do it anytime at a very reasonable cost. So this is also enabling that step. So Hyper NA, to maybe finish on that part of the story. So this is the timing. So I told you, shrink, slow down. Most probably, Hyper NA will be useful around the introduction of CFET with advanced logic because CFET will basically increase the interconnect density dramatically. We don't know exactly when we need it. To be honest, we are very relaxed about that because we're preparing the platform. We'll continue to work with our customer, and when they need it and when the business case makes sense, we will move. So right now, we have it, if you want, in the back pocket. We're ready for it. And that's the way we'd like to provide also the flexibility to our customer. So this is the 2D part. Now, one thing we see happening also when it comes to transistor density is more and more 3D integration. So if you can put less transistor per unit area 2D, you're going to try to stack them. We see that happening everywhere. And if we look at 3D NAND, if we look at DRAM, if we look at logic, one thing we have seen happening over time to enable that is wafer bonding. And we believe that wafer bonding will be everywhere. But there also, I will explain to you later, taking the example of DRAM, cost has to make sense because remember, it's not only about getting more density, it's about getting it at the lowest possible cost. But wafer bonding is going to happen everywhere. And we believe that this is a place where we can help. We believe, again, it's a significant opportunity for ASML. Marco will go a bit more into the detail of that because this is becoming important for us. But the key is when you do bonding, you take two wafers, for example, in this case, array, CMOS, and you bring them together. The problem is when you bring them together, you create a major, major deformation on the resulting wafer, which is a bit the picture you see there with all the color. This shows if you want the deformation on the wafer. This deformation is, of course, not good for the chips. It has to be taken away. You cannot take it away when you bond because it's happened when you bond. The only thing you can do is either prepare the wafer before or expose the wafer after bonding in such a way that you remove the fingerprint. That's something that Holistic Lithography can do. Why? Because we measure the wafer, we describe the deformation, and because, as we have explained to you in the past, our system is the only tool in the fab that can provide major, major correction. We show you this slide the first time in 2014, 10 years ago. Back then, we had about 20, 40 parameters we could play per exposure. Today, we have 100,000 parameters, meaning that every time we expose a die on a wafer, we can change 100 parameters in order to do it the right way. And this is, again, very powerful when it comes to deal with also bonding, pre, post-bonding processes. So Holistic Lithography, again, Marco will talk about it in detail, is very, very critical for those applications. Now, I want to finish my technology part by talking a bit about DRAM. I wanted to talk about DRAM because when it comes to DRAM, everyone talked to you like they knew exactly what's going to happen with DRAM. A lot of things will happen with DRAM. No one knows exactly what, right? The only thing we know is that the 6F-square structure that has been used for many years most probably cannot be extended forever. That everyone agrees. Then there's already a debate on when the next structure, which could be vertical transistor, also called 4F-square, could happen. And depending on the customer, they are more or less aggressive to implement it. It will also depend on how quickly they can validate it. So what we see right now is a bit of a mix at our customer between 6F-square. I think you heard Dr. Shah saying he wants to extend that as far as he can and vertical transistor. But I think there's also consensus that most probably vertical transistor will happen as well. And over time, we will look at 3D integration because if you cannot, again, put enough transistors on one wafer, you will start to stack them. But there's also a lot of discussion about how this could be done. And if you look at how it could be done, I think there's most probably two main paths. The first one at the bottom is creating 3D array, which is sometimes called 3D DRAM. But you could also create more density by just stacking 2D arrays, as we do them today, 4F-square or 6F-square over time. This is also something we see happening. So stacking array wafer to get more density is something, for example, NAND customers are going to use moving forward. So these are basically most probably the two options. And how will this be decided? Well, it's going to be decided based on the Y axis that you see on this graph. And this Y axis is, of course, cost because DRAM customers have been driving density at lower cost. They have never been driving density at higher cost. This is the curve we see with 2D array, most probably extending all the way to 2031, 2032. That's also a consensus right now. Then there is a discussion about potentially introducing a 3D array. There's been some data proving that this is possible. There's been a data point with five layers. But so far, the cost is pretty high. And five layers is not what you need in 2032 to get the density. What you will need in 2032 to get the density is about 225 layers. And if there is no cost improvement on this technology between now and 2032, the cost of the 3D array will be a real challenge. So this is a bit the debate that is happening in the industry. Can we reduce the cost of the 3D array enough to come close enough to the cost of 2D array? The answer to that depends a lot, but this is a very, very big challenge. I was talking about 30% cost improvement on EUV, right? And I was very proud of that. Here you need to improve by a factor of 100, right? So it's a bit harder. So people also talk about new material because that could be a way to make it simpler, right? But that's also material that does not exist today. In fact, material that people have been going after for a long time. So the question becomes, of course, what's happened? And what you see here is that most probably there will be a battle between a 3D array concept and a 2D array concept where we stack. Cost-wise, most probably today, the bottom has an advantage, but I think the debate around that is going to last for quite some time. And we will be, of course, making sure that we work on both. The advantage of the bottom also is that this will be using the same tools as you have today, the same fabs. So you don't need to build a new fab. You don't need to ask completely new equipments, and as long as the cost of the 2D array can go down, we can stay on the curve here. That's a very important debate. You will see us coming back to you talking about it, but I wanted to show you again that this is not a one-pass solution. I think there's many, many ideas on how to do that. So this was a bit my piece on technology. I will have a few slides on ESG. This is a summary of the commitment we have made, very simple here, which says Scope 1, Scope 2 will be done to greenhouse gas neutrality by 2025. 2025 is next year. We are on track. We will be doing that. Check. When it comes to Scope 3, I think that's a lot more difficult. So we split it in three parts: business, travel, commuting. We also want to do that in 2025. We are on track. We will do it. Check. Supply chain, this is a tough one. But because we have, of course, a strong relationship with our supplier, we are working with them so that together we can achieve the target for 2030. Huge progress being done there. We report on that in very detail in our annual report. You will see that again this year, and we have good hope we will meet that. Finally, the hardest part, which is product use, because that also includes our customer. To be honest, that's the part where we have seen a lot, a lot of progress in the last few years because all customers, everyone in the industry is really moving. We are a lot more optimistic now in 2040. It was looking a bit difficult when you set the target. Today, we believe this will be achieved. We will play our part. EUV, so I told you EUV will basically allow us to reduce power consumption. Within a 15-year period at customers, so 15 years after we ship the first tool, we will have reduced the energy consumption per wafer exposure by 80%, right? Because we work on productivity, because we work on energy efficiency, etc., etc. That's quite spectacular. So yes, EUV is, of course, initially quite energy-consuming, but the progress we have done on the technology will allow us to really reduce that by 80% by the beginning of the, let's say, at the start of the next decade. And finally, a bit of a joyful slide about our community engagement. This is something we have stepped up quite a bit in ASML in the last few years because we feel this is also becoming our responsibility. We are very engaged with the infrastructure of the community around to support our growth with education, with innovation around us. The bottom picture on the left is our, I think, world-famous light festival in Eindhoven. If you stay here tonight, you can go see it. It's happening as we speak. It's very nice. And we have been sponsoring. That's one of the events we sponsor, a lot of activity which we are very proud of. With that, I'd like to thank you. I hope that I didn't give you too much details. I'm sure I did, in fact, but this is a bit a way for us to continue to explain to you why we are doing what we do and why it is important. Thank you very much. I'd like to call one of your friends who has been switching to the dark side. Please, Amit. Thanks a lot. Thank you, Christophe. Hello everyone, to those of you in the room as well as on the webcast. I'm Amit Harchandani. I joined ASML last year to head the corporate marketing function. This is not my first Capital Markets Day. In fact, it's my sixth. The first five, the previous five, were actually spent sitting alongside many of you over the past decade. This time, it feels a bit different. In terms of my key messages, let me dive right into this. I'm going to talk about the market. The first message I would like to share with you is that the long-term outlook for our industry is promising given the role of semiconductors as mission-critical enablers of multiple mega trends in the society. In particular, and I'll go into this in a little bit of detail, the emergence of AI is a significant opportunity. And as a consequence, we do expect global semiconductor sales to grow 9% CAGR over the period 2025 to 2030 and cross the EUR 1 trillion mark in 2030. What does this mean in terms of wafer demand? We believe this translates into an overall wafer demand growth of 780,000 wafer starts per month per year over the period 2025 to 2030. The rise of AI, of course, as a leading driver to Christophe's point earlier, does translate into greater advanced logic, greater DRAM, and therefore, you could argue, is positive from a lithography standpoint. Last but not the least, we continue to expect a tailwind from what we refer to now as strategic considerations when it comes to capacity, and we still expect that to contribute up to 5%-8% extra capacity around the 2030 time horizon. Last but not the least, so we have talked on markets, we have talked wafers. What does this mean for lithography spending? Clearly, Christophe touched upon this earlier. Litho still is the best game in town when it comes to driving down cost and driving density and performance. As a consequence, we still expect the litho layers to go Low NA as well High NA across both advanced logic and DRAM. As a consequence, over the period 2025 to 2030, we expect the advanced logic EUV litho spending to grow at a CAGR of 10%-20%. For DRAM, it's even stronger with a CAGR of 15%-25%. I'll walk you through some of the moving parts over the next 20- 25 minutes. But before I do so, I just wanted to share with you and give you a bit more insight on how do we go about actually coming up with our long-term opportunity. Some of you may remember this slide. It has been shown at previous Capital Markets Days. One would be inclined to believe that you've got the low inputs and the high inputs, and all of them end up coming together into formulating the low and the high scenarios. But to be honest, even I thought that way 10 years ago. Found out it's a bit more complex than that. What makes it more complex is actually there is a plethora of inputs which go into understanding what's happening in the market out there. On top of that, you bring in all the elements associated with technology. Christophe talked about 4F-square and 6F-square, and you've got high performance and low power. It's a big blend out there. It varies by customer. It varies across nodes. You put it all together, you end up with more than 2,000 scenarios. Did not know that before I took the job. But then you put in all those scenarios, and you finally come up with the three distilled down versions that Roger is going to talk about as a part of his financial outlook. So suffice to say, just adding up all the lows doesn't give you the low scenario. Adding up all the highs doesn't give you the high. It's a bit more than that. So that's a bit about how the model works. Let's now go and talk a little bit about the end markets. So you've seen this slide. Christophe talked about it. And the reason I want to start with this slide is, yes, we talked AI, and we will talk AI. But that doesn't mean the other stuff is not happening out there. It's still happening out there. The mega trends we talked about two years ago are still very much intact. It's just that as all of us who have spent some time looking at technology know, you tend to, you know, you have to take it in the long run. Things can go a bit left or right in the short term. Eventually, they play out probably even faster than some of us anticipate in the long run. So climate change and resource scarcity, connected world, social and economic shifts, all of that is very much intact. But of course, the new kid on the block, well, is AI. And we are particularly encouraged by the rapid progress that we make in artificial intelligence. Christophe earlier touched upon the topic of productivity and what AI could mean for the wider society. We definitely think it's going to be the next big driver of productivity and innovation. There are various studies out there. I'm pretty sure all of you have looked at it from someone calling out EUR 19 trillion by 2030 to someone else saying EUR 17 trillion-EUR 26 trillion. So you have all those who are positive on AI, and so are we. But we are also very mindful that there are certain inhibitors along the way, whether it's legislation, whether it's power, whether it's ability to drive compute at a lower cost. Christophe touched upon it in his presentation as well. So AI is definitely a significant opportunity, but we need to be a bit more balanced as we look forward to it. But where we have confidence is on the chart on the right. As in case of previous computing waves, whether it was the PCs in the 1980s and 1990s, the rise of the internet followed by smartphone, we do believe the computing wave of AI will definitely have a multiplier effect on the importance of semiconductors more broadly and ensure that semiconductors continue to become a bigger part of the broader macroeconomic picture, in this case, the GDP. So then the question is, how do we think this plays out? And what I'm going to say next will not come or should not come as a surprise to you, which is that indeed, we believe in the initial wave, it would be the enablers, call it the picks and shovels, which in this case, we would call out is the servers and data centers and the storage end market, which would be the key initial beneficiary of AI. If you look at the chart on the left-hand side, we talk about units, and in particular, AI training and AI inference units. And you can see the unit CAGR is relatively muted. But if you translate that to the right towards the associated semiconductor content, you will see the CAGR there is much more significant. In fact, if I could also give you another data point, if you look at AI servers, and if you look at raw content growth, so call it transistor growth or bit growth, you're almost looking at 40%-50% for inference, 50%-60% for training on a compounded annual basis. So it's quite significant what the content opportunity means in our view for the servers end market. And as a consequence, we expect by 2030, the total sales associated with this market would be more than EUR 350 billion. That's what's happening in the servers end market. But then that needs to be then pulled into what's happening elsewhere. And if you look at the picture there, what would immediately strike you is the total number is very much in the ballpark of what we told you two years ago, which means if servers is up, the other segments are down. And that is indeed the picture as we see it today. Two years ago, we do believe there was greater anticipation of growth in smartphones, in PCs, but the broader macroeconomic backdrop has not turned out to be that supportive, particularly as it relates to growth of PCs. On the automotive side as well, some of the policy developments over the past 12 months have led us to believe that the growth is still going to come through with a slightly more muted trajectory. And last but not the least, again, to all of you who look at this space so closely are very well aware of the downturn or the down cycle that we have gone through over the past two years. But still, on the whole, if you put it together, and if you particularly incorporate for the effect of the shift towards AI, because please remember the enterprises, the consumers who will be looking to spend on AI will make choices elsewhere, you put it all together, you still have a very healthy backdrop for the semiconductor industry. So what does this mean for wafer demand? Again, let's start with the picture that all of you are familiar with, which is what we shared with you at Capital Markets Day 2022. Now, just to be very clear, the headline number we talked about back then was 2020 to 2030. However, given we are now in November 2024, we felt it's logical to talk about it in the context of 2025- 2030. Again, some of you may remember we did give a 2025 number and a 2030 number two years ago. And this was the mix we talked about with mature logic growth of 380 per month per year, advanced logic at 220, DRAM at 60, NAND at 100. So if the end market mix has changed, logically, that should also have an impact on the wafer demand associated with the end market. And if you look at the picture there, yes, there is a change. First and foremost, I would like to highlight that what we anticipate to land in 2025 is lower in total versus what we anticipated two years ago. And the two big drivers there are the NAND business, which has gone through a difficult period, which meant that the bit growth was lower, which meant that the need to add wafers was lower. And secondly, the mainstream market, which is associated with late cyclical end markets where, again, the demand backdrop remains muted. And all of you have heard some of the leading players in that market talk about the prospects there. So that means your starting point for 2025 is lower versus two years ago. But that does not mean we do not anticipate growth in 2025. We do anticipate growth, and we talked about it as a part of our Q3 briefing a couple of weeks ago. More importantly, the growth rates we believe are still likely to be very much in the ballpark of what we told you two years ago. But the big change there is DRAM and NAND, and DRAM goes from 60 to 160. NAND, on the other hand, we believe is likely to still be muted given the bit demand backdrop and translate into an addition of 40 kilowafer starts per month per year. So that's the like-for-like picture as we see it today, but there is another column I want to introduce. And the reason I want to do that is because some of you and many others have told us, "Do you really think 28 nm is advanced?" And we said, "Yeah, we get the message." And then we said, "So what do we do? This advanced stuff keeps changing every two years. I can't stand up here every two years and give you a new definition. I've been in your shoes. I hate reclassifications." So we said, "You know what? Let's go with a bit of an ASML style here. So the advanced logic, as you see, the new definition is less than equal to 7 nm, which dovetails nicely with, let's say, the chips which need EUV. So if logic needs EUV, it's advanced. And secondly, we said, if something keeps growing like this, you can't call it mature. I mean, seriously, mature was when we thought DUV would decline, which is a decade ago. Things have changed. So we came up with mainstream instead. So mainstream and advanced is the way we are going to talk about this going forward. But just to make it crystal clear and transparent, the totals all add up. It's just a shift in the way we would like to classify the logic segment going forward. And of course, DRAM and NAND stay the way they are. The total still is 780K per month per year, so that's the view on wafer demand. I want to dive a little bit more into DRAM because we talked about AI going up, driving servers up, which means it drives the DRAM growth up, as you saw earlier, and what's driving this? Well, on the left-hand side, all of you are familiar with the rising HBM content. Christophe touched upon it earlier, so did Dr. Cha in the video, and you can see what that means in terms of the AI-driven server DRAM demand out to 2030, and what you can very clearly see is the standard server DRAM is not really growing that much. The real growth engine is DDR and also HBM over the next five years out to 2030 to a level where we anticipate AI-driven demand from servers alone will go up to a million wafer starts per month per year. And you may remember on the previous slide, I talked about the total demand to be around 2.5. So call it 40% of the total number. And just before we close the topic of wafer demand, I actually want to tie it back to the transistors number that Christophe alluded to earlier. So Christophe talked about total logic transistor growth of 26%. What I've shown you here is the advanced logic component of that to make it very clear. And the advanced logic grows even faster. And if you look at this number, 32%, and compare it to the wafer numbers I showed you earlier, you can see that density is still very much alive and happening. And we are helping drive that density. Yes, Moore's Law is slowing down, but the pitches continue to come down. The density comes through, which is why we are still able to pack more transistors per wafer. And that's what this CAGR tells you. Same is the case on the DRAM side. Again, if you look at the bit growth CAGR and if you compare it to the wafer CAGR, you will see density coming through. And last but not least, the same holds true on the NAND side, but admittedly, these bit growth numbers on NAND are much more muted than some of us have seen five or six years ago. That's the end markets to wafers to transistors. Now, before we get further, we have to also talk about the other elements which go into the capacity discussion. We have talked about demand so far. There is a bit more than just end demand which drives capacity. There are what we refer to as strategic considerations. The first is the desire or the continued drive for tech sovereignty. We talked about it two years ago. In fact, that continues to only broaden, and you see a couple of new flags in there, and countries, regions continue to strive to support this industry because they recognize the importance of semiconductors. We definitely see a broadening range, a deepening range of incentives. The second element, which we did not explicitly call out two years ago, but definitely is something that continues to come up in discussions and indeed is driving what's happening out there, is the need for supply security. I was at a conference last week, and this is the latest data from SEMI, the industry association, which talks about 108 fabs, which are likely to come online, but more importantly, in all parts of the world. In fact, SEMI argues more announcements are needed to get closer to $1 trillion. But it's not just, yes, Asia continues to dominate, but it's coming up in all parts of the world. And last but not the least, of course, there is the element of competition within our customer base. Two years ago, we talked about this in the context of foundry, but if you heard what SK Hynix talked about, and if you heard what Christophe said, it's a bit broader than that. It's broadly in logic and memory. We talked about our top three customers two years ago. The picture, again, has become a bit broader. At the same time, we also have to acknowledge that particularly as it relates to foundry competition, given what we see out there in our customer base, we have to take a more nuanced view of how things are likely to shape up between now and 2030. So if you put it all together, it's still very much a tailwind for us, which means when you then think about this in the context of how capacity is built in the industry, we still anticipate these considerations will contribute towards capacity build-out. We told you two years ago that we anticipate getting to 10% by 2030. We are tempering it slightly. We think it's likely to be 5%- 8%. You could attribute to us being conservative there, but we believe that is the picture we see in front of us, which is still a very healthy level of strategic considerations, whether it's tech sovereignty, supply security, or indeed intensified competition. So that's wafer capacity. Lastly, let's talk a little bit about lithography spending, and I want to spend some time on this slide now. Christophe referred to this earlier, but let's take a moment to digest this. If you look at 2025 on the left-hand side, starting with advanced logic, what you see is a very healthy level of adoption of our Low NA technology, anywhere from 19- 21 exposures. If you think in terms of the roadmap, again, Christophe showed you the imec roadmap about the various nodes coming up in front of us. It's a broadening array because if you go back two years ago, the big driver, or even five years ago, it was smartphones, PCs, portables, tablets, low power. Whereas with servers, it's high performance. That triggers certain changes in the way you go about thinking about the advanced logic demand. But when you put it all together, remember those scenarios I talked about at the start, you end up with a range for the total exposures of about 25- 30. And within that, we expect the average High NA adoption to be around 4-6. It varies by customer. It varies by what they are looking to achieve as an end application. And it's a combination of Low NA and High NA exposures. That's why the number on top is the total number, to be precise and not to confuse you. The four to six is included, and that's why it says total EUV exposures. But that translates into a very healthy spending CAGR of 10%-20% for us over the coming five years. If you move on to the DRAM side, as you can see, next year, we expect about five EUV exposures on average, Low NA. And that is, again, blending in all that we see in front of us, 4F-square, 6F-square, and different customers have different ways they would like to go about building their designs. By 2030, it's expected to as much as double 7-10, including 2-3 High NA exposures. And again, Dr. Cha referred to it as a part of his video. And that translates into an even stronger CAGR of 15%-25%. We thought this was a much better way to get the message across to you because the key is the number of EUV layers. The key is what that means in terms of the sales numbers that Roger is going to talk about in his presentation later. With that, I come to the end of my presentation. Just to recap the key messages for all of you, the long-term outlook remains promising. We still expect to cross EUR 1 trillion by 2030. Yes, we expect this to translate into a healthy level of wafer demand with a greater skew to advanced logic and particularly DRAM versus what we thought two years ago, which is positive from a lith spending standpoint. Of course, in terms of capacity, there remain some tailwinds, tech sovereignty, supply security, and of course, competition. Last but not the least, that translates into a healthy double-digit outlook for EUV spending in the years to come. With that, ladies and gentlemen, thank you. And I will now call upon my colleague Peter to take you to the next presentation. Thank you. Thank you. Good afternoon, everyone. My name is Peter Vanoppen, and I have the pleasure to take you into the world of EUV. EUV has become mature, and that maturity allows us to innovate based on this platform that we have created. That innovation has led us into introducing new products this year. One of the examples is the NXE:3800E, which is a significant overlay and productivity improvement. But it doesn't stop there. This platform allows us to continue to innovation, continue to innovation that will bring additional overlay performance and additional productivity performance. In June of this year, we ceremoniously opened the High NA lab. I can tell you that since then, this has been a staggering success. All of our customers have been here. They have exposed wafers, and they've told us that they see the capability of the technology to lower the cost compared to Low NA on the critical layers by 20%-35%. The first High NA systems are out there at our customer, and they actually mark a significant milestone in the adoption of High NA in the semiconductor industry. The future is all about getting the cost for good printed transistors down, and we can do this by scaling the cost of EUV. This we summarize in a roadmap, and a roadmap spans a decade, the next 10 years. And what I will show you is that we will have several levers to bring down the cost on EUV. We have also, of course, an increasing installed base of EUV, and the opportunity of that installed base will be fueled by value-based services as well as upgrades, upgrades in performance, but also upgrades that will enable us to extend the lifetime of EUV. Let's put all of this in a historical perspective. Remember that EUV has introduced a significant step in resolution. If you compare the resolution where we are today compared to 40 years ago, it's two orders of magnitude of improvement. And it doesn't end there. have High NA now being there, which is another significant step in resolution. And potentially, with the introduction of Hyper NA, we will make another significant step in resolution. So our strategy, our goal here with lithography is to continue to drive this resolution down. EUV is mature. We have achieved 93.5% of availability, and you see how this availability has increased over the past years. This is a significant improvement, but it will not stop there. We will continue to improve the availability, and we are targeting in the next years to go to 95%. Availability is one part of the equation. The other part of the equation is productivity. We started out EUV in volume manufacturing at around 140 wph. This year, we brought out a product that can do 220 wph, a significant improvement. With that, actually, we have generated the capability to expose more than 3,000 wafers per day, which is a significant step if you look at where we were a couple of years ago. This is enabled by a product that we call the NXE:3800E, introduced this year. It has 38% of productivity improvement above its predecessor and 13% of overlay improvement, enabling the nm node. This is an innovative product, and the innovation is created by going to higher source power, 500 W, if you go to higher source power, you have to make sure that the system can, of course, go fast, and go fast means have higher accelerations in the wafer stage and in the reticle stage. This tool, well, I talked about productivity. The other aspect of it is overlay. On the left side of this graph, you see what we call dedicated chuck overlay, about 0.6 nm versus a spec of 0.8, on the right side of the sheet, you see the historical performance in matched machine overlay, today, we are achieving sub-nanometer levels on matched machine overlay. We are introducing this system at all of our EUV customers, all of our DRAM customers, logic customers, and foundry customers in the next year. It doesn't end there. We are already working on the next generation. The next generation will be introduced early 2027, and this tool will enable another step in productivity and another step in overlay targeting 1.5 nm node. Same type of innovation, but then again more. We go to 600 W of EUV power, and we go to another step in accelerations, wafer stage and reticle stage, enabling the tool to keep up with the source power that we generate, and it doesn't end there for this platform. We will continue innovation on the platform to introduce more productivity and better overlay going forward. It doesn't end there for EUV. We will expand our portfolio, and this portfolio will be expanded in a way that we like to use that portfolio to create flexibility for our customers to have a lower cost of good printed transistors. Doing that, we will focus on yield. We will focus on resolution. We will improve the accuracy. We will improve the productivity and all that while optimizing cost. High NA window of opportunity. It is now. If you look at this logic roadmap, we talked about single exposure. We talked about double exposure. Single exposure of High NA we can use today. And we can extend that opportunity into the 0.7 nm node and probably even beyond that. I'd like to introduce a bit more you. High NA fundamentally improves the process complexity. I told you already it improves resolution. It will bring additional accuracy capability. Because of the single patterning capability, it will bring productivity. Let me talk about it in more detail and summarize the technical values and the customer benefits. 0.33 NA versus 0.55 NA. It gives you the opportunity to shrink the device density by a factor of 2.8. It will enable a contrast improvement of 40%, which has a big impact on dose and which has a big impact on local CD uniformity, the integrity of the pattern. This will lead to benefits for our customers. These benefits for our customers are foremost the patterning cost reduction. The patterning cost reduction is fueled by three main things. First is enabling single exposure. Second is dose reduction. Third is the ability to go to two-dimensional designs. Process simplification leads to defect reduction. Defect reduction has a positive impact on yield. Single exposure has an impact on cycle times, less mask steps. Less mask steps leads to a better optimal use of the fab space, so these are the benefits that our customers will see when they start using High NA. High NA is here. As I already said in the introduction, we ceremoniously opened the High NA lab in June, but June was the end and the beginning of a journey. It was the end of the development cycle. The development cycle for High NA took us a decade. We started designing the tool back in 2014, and soon after the design, we started manufacturing the first modules. Of course, when you manufacture them, you have to integrate them. You have to make sure that they work. You have to qualify them, and after that, in the period of 2023-2024, we did what we called system integration. That is a very important step when you put all the functionality together and you make sure that you get to this resolution, this accuracy, the speed that you need to make this technology work and led to the first good exposed wafer the High NA lab. This Joint ASML High NA EUV Lab is an important for High NA. all of our customers have started exposing wafers, and they do that to make sure they start learning on this technology, learning in terms of processes, learning in terms of masks. And with that, they hope to reduce the time from the first process development to when they can start using this technology in high-volume manufacturing. You see on the left side of this graph that by the end of this year, our customers together, both DRAM and foundry customers, will have exposed about 2,000 wafers the High NA lab. These are 2,000 highly valuable critical wafers that help them understand the capabilities of the High NA tool. The first feedback we get from our customers is actually extremely positive. They're telling us that they very well see the contrast improvements, the imaging capability of the tool, even to the extent that they're saying it's a bit better than what we expected. This is also illustrated by some of the statements made by our valued customer, Mark Phillips from Intel, who presented at BACUS Conference last September. He's saying, "High NA is there, and the tools are healthy. The ecosystem is ready to use High NA. The expected benefits of High NA are evident, and the timing of High NA is right. It's right in a sense that it's on time to avoid complex mask splits for Low NA." Back to the fundamentals. High NA is a higher NA, better resolution, better contrast. Better contrast leads to lower dose. Lower dose leads to higher productivity. Higher productivity leads to better cost. The other aspect is better contrast leads to lower defects. Lower defect density leads to better yield. Better yield leads to better cost. Other fundamental aspect of High NA, and Christophe alluded already to it, is the capability to go to two-dimensional designs. In the animation and drawings, you can see if you do interconnects with Low NA, you have limited to one-dimensional structure. And to connect all of these transistors, you will have to do this in multiple layers. You can see this here. On the middle picture on High NA, you can actually connect these transistors in one go. And with that, you reduce the cell size, the logic cell size, and you probably can also reduce the number of metal interconnect layers that you require, again, leading to a cost benefit. Theory is one thing, but data speaks for itself. The upper row is exposures we did in the High NA lab. This is a relevant pattern, contact hole pattern for DRAM, and it shows pitch 40 all the way down to pitch 28 on the upper row. The lower row, you see the corresponding Low NA exposures, one-on-one comparing the two to each other. A few things become apparent. High NA drives resolution down to pitch 28, and probably even beyond that is possible. And the other aspect is, and you can see this in the number, dose and local CD uniformity, there is a significant reduction in dose and a significant improvement in local CD uniformity with High NA. And what I did is I recalculated the dose that you would need on Low NA if you would print these Low NA pictures at the same local CD uniformity as High NA. You see that the capability that you can generate with the optics, you would otherwise need with excessive dose, and excessive dose, of course, is creating a problem in cost, and therefore, I also calculated what the cost advantage of High NA is compared to Low NA at the same local CD uniformity, which approaches 50%. Let's now look at a few logic use cases. This is a logic use case, pitch 19. If you want to print this with Low NA, you would need three mask splits. If you do this with High NA, you can do this in one go, leading to a cost benefit of 35%, fueled by the productivity change, of course, but also fueled by the process simplification. Another relevant pattern, this is what we call random vias. This has a critical dimension of about 30 nm. This is a case where you see two mask splits being replaced by one mask on High NA, leading to a cost benefit of 20%. Then, if you look at random vias at the pitch where you can compare directly Low NA and High NA, the evidence is again there, better capability in terms of local CD uniformity, pattern integrity, as well as dose and productivity. Let me extend that again to DRAM. This is a DRAM critical layer, pitch 30 or 15 nm contact holes, hexagonal pattern. This is something where we would need three masks, two EUV masks and one DUV mask, which we can replace with one exposure of High NA, generating 35% of cost benefit for this particular layer. One-on-one comparison, similar conclusion, local CD uniformity improves significantly, dose significantly lower, leading to a higher productivity. Now, one thing I have to about High NA is that because of the optic, you are limited to half-field exposures. If you look at half-field exposures for DRAM, where we typically have small die, this will lead to the fact that to generate a full field, you will have to do two masks, two times the same mask to generate a full field. If you look at the logic case, where some of the die are larger than the half-field, you have to do something which we call stitching, meaning that you have to have a mask A and stitch that mask A to a mask B. We wanted to investigate how well we can do stitching, and from these SEM pictures, you can see that actually is almost not able to see where the stitch line is. That's why I put a line on top of it. So this means that the fundamental capability to do this is there. This is an engineering problem. We can just develop processes to do stitching on the High NA tool. I talked about Low NA. I talked a lot about High NA. But let's now talk about the future of EUV. The future of EUV is affordable scaling. And for the affordable scaling in the next decade, we're going to do a couple of things. We're going to continue the innovation on our current Low NA and on our current High NA platform. That innovation will be fueled by the source power, productivity increase, will be fueled by overlay improvements, and this will span into the next decade. But we will also make a transition. We will make a transition to a high productivity common platform. And that will enable us to drive the cost per exposure down to 30% towards early of the next decade. How does this work? This works by an innovation which we call a modular frame architecture. That modular frame architecture is enabling us to fit optics, which are very different in size and in a Low NA optic a High NA optic, onto the same tool. With that, of course, we can generate a lot of commonality on these two product lines. And we can benefit from the innovation on this platform, which we will need. We will need to make the reticle stages and the wafer stages faster and faster. We will have to do this just once, and both product lines will benefit from this. The other consequence of this architecture is that we can fit the Hyper NA optic on it. Christophe already alluded to it. By fitting this Hyper NA optic on this high productivity common platform, we significantly reduce the lead time to get Hyper NA out to the market. When we talk about scalability, it is all about productivity. So when you have a platform that can cope with the productivity challenge, you need, of course, the horsepower, or in this case, the source power, to generate all of the photons that are required to generate the productivity. Today, we have products that can generate 500 W or 600 W of EUV source power. We have demonstrated technology to go to 740 W. And we have the ideas to scale this to one kilowatt. Effectively using photons means that you need to make sure that the transmission of your optics is right. We already talked about the innovations in High NA optics. And we are now deploying that innovation in Low NA in a new POB, a new projection optics for Low NA, which we call the high transmission projection optics. That high transmission projection optics will have a factor of more than two better transmission. So that means that a lot more photons that we generate in the source will end up in the wafer and will lead to the productivity. With High NA, we do it slightly different. There we are improving the illuminator. And we are innovating in an illuminator that we call the flexible illuminator. With the flexible illuminator, the total projection optics system will have a transmission increase of 1.4x. And one of the other benefits that are generated by this flexible illuminator is the ability to even further scale the contrast and resolution compared to the tool, the High NA tool as we have it today. This leads to a productivity roadmap. This productivity roadmap is leading us to productivities going all the way up to larger than 450 wph for single-expose Low NA. Now, let's compare that to single-expose High NA, which is depicted in black. This goes up towards 300 wph. Now, if you want to think about cost-effectiveness of High NA versus Low NA, then you have to compare High NA single-expose to Low NA double-expose. Low NA double-expose is the lower light bluish line. You see that in terms of effective productivity, High NA is outperforming the Low NA tools for this effective productivity, leading to the cost advantage for these critical layers where we can deploy High NA. I talked about Low NA innovations, maturity. I talked about the readiness of High NA and how our customers are starting to use it. I talked about the scaling of EUV and how to finalize about the installed base. The installed base of EUV is growing, and this creates an opportunity for us and our customers, and that opportunity is fueled by us improving continuously the availability of the tool, by us improving the cost per exposure, by us making sure that we can extend the lifetime of the tool towards 20 years, and by making sure that the tools that our customers have in the installed base are going to be able to cope with the upcoming nodes, and therefore, we will deploy performance and productivity upgrades. With that, I'd like to summarize. EUV is mature. We have innovations ongoing in Low NA. The High NA tool is ready. We have an affordable and scalable EUV roadmap for the next decade. We are deploying service models and upgrades that will fuel the opportunity in service. With that, I would like to thank you to listen to this presentation. With that, I'd like to introduce Herman. Yeah. Thank you, Peter. Thank you. Good day, everybody. I'm Herman Boom. I'm in charge of the business line DUV. Today, I'm going to talk to you about the DUV portfolio, the DUV business. As Christophe already said, it's a lot about innovation. Also in DUV, it's still about innovation. It's about innovation of performance. It's about innovation on productivity. It's also an innovation on cost. Before I go there, let me go to a few key points with you. If you look at DUV, DUV is and will remain the workhorse of the industry. In that context, there's a very important role to play for immersion. We keep on supporting our customers with a high-end immersion line and a mid-critical immersion line targeted at overlay and productivity improvements. If you look at the dry portfolio, then we have our XT and NXT systems platform that keep on providing full flexibility to our customers in terms of performance, but also in terms of cost effectiveness by building on commonality and operational efficiencies. Very noteworthy is that in the dry portfolio, we're also extending our i-line portfolio with a wide field scanner, the XT:260. Now, I will be talking about that because it's an important one also in the context of advanced packaging applications. We are optimizing our installed base. We keep on providing a diverse portfolio of service offerings, upgrade offerings, and by doing so, actually enabling our customers to keep our systems running, to keep their installed base running for more than 20 years, and we'll be talking about that as well. Now, we heard Peter and Christophe talk about EUV, and EUV by now is the standard for almost all critical logic and memory layers, but there's a huge amount of layers. The vast majority of the layers is still printed by DUV and using DUV technology, and that's also reflected in the number of wafer exposures that we see. If we project that from today into 2030, you see that we are almost doubling the number of wafer exposures, and that is supported by different applications and different market segments. On the left-hand side, you see here the advanced market segments, reclassified, as Amit already said, using all EUV. But you also see there that DUV is present in these advanced segments, supporting, you could say, the EUV applications. All of that being done at 300 mm. On the right-hand side, you see the mainstream segments. You see a much more diversified application space. You also see that this is the DUV space where we not only have a 300 mm wafers, we also have 200 mm wafers, we have 150 mm wafers even, and we have many more different applications that we are supporting with our product portfolio. And that's also all those different applications, they also lead to some of the wafer growth that we see. And if you look at the different wavelength segments in that portfolio, then you actually see the steady growth. But if you project it outwards towards 2030, you see that part of the growth is simply given by sheer volume, the fact that we need more wafers being printed. But there's also a part which is driven by more layers, a bigger litho spend, if you like, in those applications. And if you look at that, and we look at how we actually deliver the different value there, then we go back to the equation that Christophe showed. Right? There There at the top side, we see the different value drivers. And at the bottom side, we see the different cost drivers, if you like. Now, I'm going to talk you through what we do with the DUV portfolio by first addressing how we create value, how we create resolution, accuracy, but also productivity. And I'm going to do that by taking you through the portfolio of DUV. And if you look at that portfolio of DUV today, then we basically have four wavelengths, or we have three wavelengths, starting with i-line. We have KrF, we have ArF, and we have ArF again in the form of immersion. And then we have two platforms. We have the NXT platform, and we have the XT platform. And I would like to walk you through the different wavelengths and the different things that we're doing in terms of innovation on those wavelengths, improving cost effectiveness for our customers. Now, let's go in and start with immersion. If we look at immersion, then the ASML immersion portfolio is the backbone of today's industry. On the left-hand side, you see the total number of installed systems. There's well over 1,000 systems that are out there in the total world capacity. And the vast majority of that has been installed by ASML. And we've come to those numbers by growing our installed base since the mid-2000s already. Right? And that growth has been supported by innovation on productivity as well as overlay. If you look at the last five years, then 92% of the added wafer capacity has been installed by ASML. And if you look at that more closely, then actually you see that there's a difference in the different requirements that our customers have. We have the high-end where next to productivity, accuracy, overlay performance remains very critical. And that we see mostly applied in, for example, the memory space. But we also have a big chunk which we call the mid-critical, our NXT: 1900 series, which is mostly targeted at productivity and still at very impressive performance levels. I already told you that we came here by continuous innovation, which you see by the different models that we released in the different years. You see that at the bottom of the page. It doesn't stop there. We keep on investing in immersion technology to further address performance, to bring the overlay down even further, but also to improve cost of ownership by improving productivity. On the top chart here, you actually see our high-end immersion. You see the different models that we have been introducing. You see that also the matched machine overlay has been going down all the way from 1.5-1.0 nm in the 2150 that we will be releasing later this year. The productivity hovers around the 300 wph mark. Now, if you move towards the 1980, then you actually see an overlay of about 2.5 nm, which is sufficient for a lot of the markets. What we see is more geared towards productivity. We're having levels there of 330 wph. And we're also developing our next immersion system, which will be north of and have a larger productivity than the 330 wafer hours that we have today. Now, if we look at high-end immersion, and I already showed that we started with that like a big five years ago, then we see that we have a solid adoption of those systems by customers. We have a very solid installed base. By now, we also have shown that when we install those systems within two or three weeks after they have been installed in these high-volume manufacturing fabs, our systems ramp up to their maximum productivity to around 5,000 wpd. At the same time, over the years, with the different models, we have been improving the overlay all the way from 2 nm down to 1.5 nm to 1.3 nm. And we'll be making another step to 1.0 nm later this year. So it doesn't stop there. Later this year, as we speak, actually, we are in the midst of the qualification of our next high-end immersion system, the NXT:2150. It's supporting even tighter overlay requirements, but it also supports improved cost matching between EUV and DUV. There's a whole slew of different technological innovations on board, ranging from heating controls, temperature controls, new metrology, new sensors, but also very important new optical correction elements. And these optical correction elements are also very important. I will talk about it in the next slide to actually apply additional corrections. So on this table, I have the 2100. It's still geared at 295 wph. And we're improving productivity somewhat toward 310 wph, while improving the overlay performance. Now, I talked about these optical correction elements. And they are important, particularly in the context of bonding and the correction of bonding that we needed. So Christophe already showed that when we bond those two wafers, actually we get mechanical deformations in those wafers, which lead to overlay errors. We can measure those overlay errors using metrology. And then we feed that data into the scanner. We feed that data into the scanner so that we can use it to calculate the corrections that we have to apply to the pattern, to the image, and by doing so, we also need the correction knobs to be able to tune that pattern image, and by applying more of those knobs, we can actually get it to a larger correctability. That correctability has led to data, like showing also here today, that post-bonding, you would have a 15 nm overlay error. After applying these corrections, you have a potential to go down to 2.5 nm, so we believe that bringing these additional correction knobs provides a lot of value and a lot of correction capability in that space. Now, let's go to the next part of the portfolio and talk about the dry portfolio, very specifically about KrF. In this part of the portfolio, we do not only have the NXT platform, we also have the XT platform. If we look at those two, then actually those two platforms both serve high-volume wafer fabs, but with a slightly different flavor. You look at the XT fabs, or what we call the high product mix fabs, they actually look for versatility. They look for flexibility. They like to configure their system with all kinds of different options, 200 mm, 300 mm, in such a way it perfectly suits their needs. On the right-hand side, you see the NXT. The NXT is a high productivity platform. It actually suits best in what we call low product mix fabs. Low product mix fabs, meaning all 300 mm, not running an enormous amount of different products, just making sure that you get the best out of this big productivity that this platform provides. That's not only happening today. We also see towards the future, if you look at the new announced fabs, we still see a lot of interest and a lot of application of both platforms in all these different fabs all across the globe. Now, if you look a little bit closer into KrF, and we look into our latest NXT:870 KrF system, then we've seen that system have a solid adoption, a very solid and rapid adoption with a lot of productivity, proven productivity, and reliability. The reason we could do that is because we built it on an NXT platform, an NXT platform that we already know from immersion and also from ArF before. Now, we have seen a very solid adoption, and we've seen actually record numbers in terms of productivity on 13-week moving averages, well, spiking at 7,000 wafers per day. That's only possible because the system is very reliable, actually providing availabilities north of 95% continuously. It's not where we're stopping. So this system is running at 330 wph, actually. As we speak, we have been qualifying our 870B, which is planned to actually have a productivity of 400 wph. This system, we are qualifying as we speak. I'm very happy, actually, to be able to tell you that we had the first sign-off of this system earlier this week. This brings me to the next part of the portfolio, i-line. On i-line, we've been extending our portfolio. We plan to extend our portfolio next year with the XT:260. The XT:260 is a bit of a special system in the context of how we normally develop our systems because it's a very high productivity i-line scanner. The reason we are able to do that is because this system has a larger exposure field. The larger exposure field does two things for us. The first thing it does, well, if you have a larger exposure field, you simply need less exposures to fill up a full wafer. It cranks up the productivity significantly. We're talking about 350 wph, which is the industry's highest productivity on an i-line system in this segment. But the other thing which it does for us, it has this larger exposure field. And particularly in advanced packaging, where interposers are printed, the typical interposer size today is about 2x of what an exposure field of a regular scanner will be. So that would require stitching. With the 260, you can actually print this in one go. And even towards the future, when interposers start growing, you can actually still print this in one go, maintain your productivity, whereas a normal 4x stepper or scanner would fall down and would actually reduce in productivity because it would end up swapping masks all the time. And that's being shown in the graph on this slide. Now, I've been talking a lot now about our portfolio. I'd also like to give you an update on what we're doing in terms of addressing cost, keeping things affordable, and also staying competitive. I'm going to give you a peek into what we do with commonality, configurability, also infrastructure base management. To be able to do that, I'd like to start with commonality. Commonality is a very important part of our strategy. Interchangeable. We can have the opportunity to upgrade our systems later quite easily. During service, during the life of a system, lower OpEx, very important also, we can repair and reuse many more of our parts because they are the same. That leads also to higher availability. Now, if you look at what we do for cost-effectiveness, this is not only limited to product design. We're also engineering quite a bit on operational efficiency. One of the examples I'd like to show you is one where we are moving transport from our systems, from airplanes to the boat, which requires quite a cross-functional coordination. It brings actually down the carbon footprint of transportation a bit down at about 95% by taking it from a plane into a boat. And I'd like to show you what you did based on a video. And I'd like to start the video right now. Thank you. Join the next sustainability wave. ASML extended its transport capabilities to include ocean freight, delivering a 95% reduction in greenhouse gas emissions and a significant reduction in transportation costs. It begins with a team of experts across engineering and operations who redesigned the entire logistics process and developed new capabilities with a focus on quality and reliability. Extensive packaging protects climatic and mechanical-sensitive parts from environmental conditions. A specially designed reefer container controls temperature and humidity. Onboard sensors monitor shocks and vibrations at every step of the journey. Operational diligence and supervision continues upon arrival at the Port of Rotterdam, where ASML established special agreements with freight forwarders to allow for direct loading from our truck to the ship, tightly controlling any shock or vibration during movement. ASML containers are purposefully placed below deck, protected from direct sunlight, water, or wind exposure. All of these critical steps protect the quality of our shipping process. At arrival, we replicate the same quality process and procedural controls followed at departure, including direct unloading and inspection. The team's relentless efforts and preparations all come together with on-time delivery to our customers. We celebrate the first of many DUV systems successfully shipped by boat, validated by data collected throughout the entire journey that guarantee quality. ASML is committed to reducing our carbon footprint. Are you ready to change for the better? Join us today and let's move to ocean freight and realize the sustainability and cost ambitions for your organization. Because it matters. Yeah, and talking about shipping systems, this was just one. But ASML has been shipping systems actually for a long time. And so I'd like to talk to you also about our installed base. If you look at the number of systems that we have out there by now, it's over 6,000. And we already talked about and said that we like to sustain our installed base and actually extend the lifetime of our installed base, increasing the longevity. And in order to do that, we have a whole portfolio. We have systems out there which are already 30 years old. So we have our PAS platform, which we started shipping in the mid-1990s. Then around the 2000s, we started shipping our AT platform, which is still out there, followed by our XT platform. And in 2009, we shipped our first NXT system. So throughout the lifecycle of those systems, we're offering different service options. We start with warranty, regular service. Then customers also have the option to go what we call up value up service, which means that we do service beyond the normal specifications that we have, suiting individual needs that customers would have. We can also do field upgrades with that, increasing the intrinsic capabilities of the system, for example, productivity, but it could also be overlay performance. Then we move into an extended service where it's very important to also apply refresh. So there's some wear and tear on those systems after 15-20 years. We offer refresh packages. We see quite some traction with our customers to keep their installed base live, vibrant, and on performance. Also, trade-in and buybacks. If customers think, "Hey, from a fleet optimization point of view, I like to actually trade in the tool, go for something different," this is also something we will entertain, and then, of course, beyond 20 years, again, refresh has become important, and also there, we offer the different service and upgrade options, and if you look at that, what that does for the opportunity out there, then this whole installed base provides an opportunity based on this expanding service and upgrade portfolio, and in here, you see the different revenue expectations that we have based on the portfolio that we have in place, which splits in regular life services, extended life services, field upgrade revenue, and also trade-in and refurb revenue. I'd like to give you one example of what we do, for example, for immersion. This is a slide where, from left to right, you see actually the productivity going up, and from top to bottom, you see actually the overlay performance improving. You see the different systems that we have shipped over the years plotted in this graph, and what's now important to understand is that we can bring basically every system from every performance down to, well, we can upgrade it in terms of productivity. We can upgrade it in terms of overlay, and you also see these little green bars. We can also provide wafer-per-day upgrades. Wafer-per-day upgrades are things like where we provide services, but also upgrades where we integrate in the customer process our systems together with the rest of the equipment in such a way that we actually get more wafers out per day. Now, you see this here happening all the way from the 1950s, 1960s, all the way to the 1980s. The same applies for the high-end immersion, where we can also upgrade from a system that you once bought to the latest and greatest that you're interested in. Now, with that, I'd like to conclude. And I will not go into all these details. I think I'm in between you and the break. So I'd like to thank you very much. And I'd like to call Skip on the stage. All right. We're about halfway through the program. Two hours, I know, is a lot of material. So we want to get you recharged for another round of two hours of material. So what you want to do is, if you can come out and go down either side door here at the bottom, we have some drinks and snacks outside. But we are going to ask you to be back here at 3:30 P.M. And so for the webcast, we'll start again at 3:30 P.M. You should see a countdown clock on your end. We'll see you shortly here. Please be back at your seats at 3:30 P.M. Thanks. How are you doing? Good to see you. How are you doing? All right, thanks everyone for making it back on time and keeping us on schedule, and welcome back for everyone joining via the webcast. Let's continue the program, and I'd like to bring up Marco to give us an update on Holistic Lithography. Thank you, Skip. Thank you. Good afternoon. I'm Marco Pieters, responsible for Business Line Applications, and this afternoon I'd like to give you an update on our Holistic Lithography solutions and the opportunities. Before I start with a couple of key messages, I first like to explain what Holistic Lithography is about. And actually, we're focusing on improving accuracy and pattern yield for our customers. And we do it in the following way, which is depicted by the triangle on the left. Peter and Herman already discussed about the scanners, and they also show that these scanners have an advanced control capability: manipulators, optical elements, etc. And with Holistic Lithography, we actually complement that with, on the other hand, computational litho and metrology that gives us basically models that we use to already predict the behavior of the scanner upfront when we're preparing masks. On the right-hand side of the triangle, we complement it with metrology and inspection, both optical and e-beam. We use those systems, as you will see, to basically get a lot of measurements on customer wafers in order to steer that advanced correction capability on the scanners. Now, if we talk about accuracy, what is this? This is basically driving improvements in overlay and edge placement errors via this computational litho, physical models, but lately also AI, metrology, inspection, and that scanner optimization. We've talked a number of times about edge placement errors. Basically, what that is, it's the tolerance that we have between the design that customers basically have on the mask and what actually happens on the wafer. That difference, that's an edge placement error, and that we need to, of course, keep within certain tolerances. The second part that we focus on with Holistic Lithography is pattern yields, and there we are driving cost-effective metrology and inspection, both for 2D and 3D devices, as you saw also in the imec roadmap shown earlier by Christophe, because that's key for early yield ramp and Holistic Lithocontrol, and on that part, I'll also show our significant progress on our multi-beam e-beam inspection system and the opportunity for driving that system into high-volume manufacturing, and there, the first application that we will see is the so-called voltage contrast inspection, but more on that later on, and after that, we think there's more opportunity by measuring smaller or trying to find smaller 2D defects and 3D structures that require actually buried defect inspection. Next to that, we also will enable front-end 3D integration wafer bonding with metrology and control solutions to basically meet our customers' requirements on overlay because we see there is a challenge of the wafer bonding and the deformation that is happening on those wafers. Overall, if we look to the total Holistic Lithography business, we expect that to grow with a CAGR of about over 15% in the next years from 2025 to 2030. That goes together with strong gross margins. Now, if we look back to the value equation that was shown before, Holistic Lithography basically focuses on pattern yield and accuracy, and this is where our product portfolio is active. We can be a bit more specific, but I will do that first by looking at the logic roadmap shown by Christophe already from imec, and this roadmap has a couple of components. The first component, it shows that 2D shrink will continue, and as edge placement error is basically also linked to that shrink, we'll actually see that that shrink is driving tighter and tighter control on edge placement errors. Secondly, we've also seen that 3D structures also are part of that roadmap, and especially with the introduction of, for instance, the backside power network, we also see that the backside metal pitch is reducing over time, and that in itself is also giving us tighter and tighter requirements on post-bonding overlay requirements, so how do we now want to tackle those challenges? As I said, we're focusing on pattern yield and accuracy, and we do that by four groups. The first group that we're focusing on is scanner and process control software. The drivers there are with transitioning to EPE, pitch shrink, but also wafer bonding. There the trend is that also it's not just EPE, it's EPE on top of overlay and CD. If we look to high-volume manufacturing, it used to be only DUV. Peter said already, EUV is mature, EUV is there, but moving forward, High NA will be part of that. So also that means our solutions need to go all the way from DUV High NA. in terms of the correction capability, we showed the graph earlier today. I will go back into more detail later on, but there we go from, let's say, low order corrections, a limited number to correct to very high order and a lot of correction capability. If we look at computational lithography, there the drivers are all about the accuracy of litho and edge models, and that goes together also with compute cost. So what are we doing there? As I said, we started off with physical models. Those have been complemented by deep learning and AI techniques. In terms of mask patterns, it traditionally was all rectangular. Now we go to more freeform patterns. And in terms of compute cost, where traditionally we're only looking at CPUs, we have been also adding there the use of GPUs and hybrid platforms to basically drive down the cost of compute. And going to metrology, both optical and e-beam, and metrology is all about accuracy, precision, local stochastic effects, and of course, at the right cost. Some of the trends that we see in optical overlay, we always have been measuring on targets, but now we also see opportunities to start measuring on device. And of course, with the tightening requirements on overlay, we go to more and more sampling. On the e-beam side, there we go from a small field of view to a large field of view, and that actually enables so-called massive metrology, where we can get massive amounts of CD data from wafers that allows us actually to optimize not only CD, but also edge placement errors. And finally, on inspection, where it's all about resolution, throughput, being able to measure both electrical but also buried defects. And there is a trend where traditionally it was optical. We have been moving to single e-beam systems, and you will see today, I'll also show what we have been doing on multi-beam systems, including the application of voltage contrast. And these four segments, we also can look at the TAM associated with that, and we see actually by 2030, we actually envision there a doubling of the TAM compared to where we were in 2023. Christophe showed a slide before. The lithotool is the only tool in the fab that is basically capable of correcting other process errors, the process fingerprints. Why is that? Actually, every wafer that goes into the lithotool gets first measured on the metrology stage. We have a good idea of how that wafer looks like. Secondly, every field of every wafer is exposed field by field. That means we can actually optimize the settings of that scanner for that particular field. You see in the picture, we have a number of elements, actuators, manipulators that we can actually customize for that field. Over time, you see actually here that correction capability, how it increases over time. Today, if we look at all the degrees of freedom that we have, that we can actually optimize per field in the lot, that gives us about 100,000 degrees of freedom. Now, how do we use that? Well, what you see here in the dot and the lines, you see here the trend of basically the scanner capability in terms of overlay. We simply use the scanner as it is, and you get this type of overlay. Of course, here you already see a significant improvement in overlay over time. But if we then start using these manipulators, that correction capability to really optimize for product wafers, we actually see that by doing this in a holistic way, we can actually further improve the overlay capability that customers get on product. And of course, you see with more and more process effects coming in, the importance of Holistic Litho only becomes more. And this is an example where we focus on overlay, but we can actually extend that by optimizing towards edge placement error. And I think that's another opportunity to explore because we do see that that metric of edge placement error has a significant better correlation to yield. So this is something that we will be exploring, and I'll show you an example later on. If we talk about computational litho, as I said, it's all about the accuracy of the models that we have. So before a mask goes into production, we do a so-called optical proximity correction. Traditionally, let's say 10 years ago, when the world was only using DUV, we did it with physical models fed by a limited number of metrology gauges, a limited number of parameters, and we got a certain accuracy at a certain cost. With the introduction of EUV, there was, of course, a need for a higher level of accuracy. We did that by the following way. We have extended those physical models with AI techniques, deep learning techniques were fed by more and more metrology. By doing that, you can see the white curve, the accuracy actually went down significantly. More important, well, we had got the accuracy down, but if you look at the cost, it was still at an affordable level. So if you look at the enormous increase in the amount of model parameters, the amount of metrology needed. Overall cost was still kept affordable. As I mentioned, we've used that scanner capability to optimize overlay, but this is a project we have been doing with one of our customers, SK Hynix, where we actually did an optimization that we called EPE Aware. So what we have been doing, if we follow a wafer through the line in a very simplistic view going from left to right, of course, first of all, we make sure that the mask to pattern that first wafer is optimized with computational litho. We exposed the first layer or layer N for that matter, and after exposure, we can actually measure with e-beam, high-density e-beam, global CD, but also line edge roughness, so that gives us basically imaging information. Then we expose the second layer on top of the first one, and then we can measure the overlay between the two layers. We do that with our optical system, and thirdly, then we can again characterize that second layer also with e-beam metrology, giving us the global CD, but also the local CD and placement errors. If we then combine these different data sources, we basically can reconstruct the edge placement errors, as you see on the right-hand side of the screen. That is an input to basically feedback to the scanner again. From those edge placement errors, we can actually see how the next lot should be tuned in terms of overlay parameters, focus parameters, dose parameters. This is something that we will be exploring more moving forward. As I said, this all depends on having metrology. If we look to our optical overlay system, so-called YieldStar, we actually see that over time, where in the purple line, you see actually the increase in the amount of data points that customers need to sample in order to meet overlay requirements. Of course, we have been following that trend, but more important is with that platform, we were actually able to reduce the cost of a single measurement by about 30%-45% in four years. So you see, while the amount of sampling goes up, we were able to keep the total cost under control. Moving forward, we see an opportunity there for even more sampling. 2D shrink, as I said, with lower pitches, lower edge placement error tolerances, we need to measure more. I think we mentioned it a few times today. We also see that with wafer bonding, we need more and more data points to basically capture what we see on wafers, in some cases even over more than 2,000 points per wafer. Now, talking about our YieldStar platform, earlier this year, we actually celebrated the fact that we have now an installed base of 1,000 systems. Actually, this shows the need for having high-end metrology that can be used to basically optimize the scanners. Looking at inspection, e-beam inspection, as I said before, if we look to the landscape of inspection, and if we look here at the landscape as a function of defect size, if we look at defect sizes over 10 nm, traditionally, that's all physical inspection done by optical solutions. Going below 10 nm, the resolution of optics is no longer sufficient, and there is the opportunity for e-beam. But with e-beam, it has more capability than just physical inspection. With e-beam, we can also do so-called voltage contrast inspection and see-through, so we can actually also measure buried and electrical defects. Now, if we look here at some of the latest trends, we do see, of course, that progress has been made in optical inspection, but we also see that new nodes really require higher resolution to capture defects well below 10 nm, and you see it in the middle of the slide; it's also confirmed by a quote of one of our customers. We basically say, "The defects that I see here in that light blue oval, they cannot be detected by any optical inspection tool regardless of the inspection time." And the other thing what we see is that because of the more complex 3D structures that fuel the need for voltage contrast inspection, it started with NAND, but it will soon now also move to DRAM and logic. And I'll talk about more on this voltage contrast inspection. So with voltage contrast inspection, what it does on the top left, it actually detects defects between layers that cause an electric open or a short. So with the e-beam system, we can actually find those defects, as it's heavily used already in 3D NAND. And we also see actually that this type of inspection also correlates very, very well with edge placement error. So it's a very good proxy for yield. On the right of the slide, you actually see here our presence in that market in the last couple of years. So this we have been doing with single beam systems. Now, of course, a logical step would be to basically multiply the amount of beams, what we call multi-beam. We have been doing that, and the product that we have now in the market is called the eScan 1100, and that system has 25 beams. The first thing what you could see, of course, and that's the bar chart on the graph here, is that that system's capability basically gives us a factor of 10x more throughput compared to a single beam system. So you see every bar here represents a layer that's being measured at one of our customers, either a logic customer or a DRAM customer or layer. Now, next to where we are today, about 10x, we also have plans to further improve those systems. So early next year, we will be releasing a throughput upgrade to those systems, and you can see in dark blue the projection that we have for the next step that we can make in productivity. So how do our customers use that productivity? It's not that they basically start measuring shorter. No, what they do is they typically spend the same time on measurements, but then in a given timeframe, they can cover 10x more of the wafer. And why is that important? If you cover 10x more of the wafer, you are able to find defect fingerprints. And the earlier you detect defect fingerprints, the faster you can correct them, and the faster you go through your cycles of learning. And we try to envision this here in the coverage between a single beam system, where you see in this particular case has 0.1%-0.2% coverage, where on the eScan 1100, the multi-beam system, we already have 1%-2% coverage. Now, today, that system is out there. By the end of the year, we have over 10 systems installed at over five customers, and they're all being evaluated and qualified to use this in HBM. Another data point, and this is collaboration together with Samsung, it actually confirms here also that by using this eScan 1100, they actually had a 7 to X larger wafer coverage at 60% shorter cycle time. So in this particular case, they even optimized the wafer coverage that they need versus the cycle time that they thought was needed for that. And also here, you can see with this wafer coverage, you can imagine you're able to detect fingerprints significantly faster. So this is the system that we have today. But of course, there's always a roadmap attached to it. And here you see our roadmap on our e-beam systems. In the bottom, you see our single beam systems, eScan 460 that we have now at our customers, eP5 XLE. And we will continue to upgrade these systems and make them more efficient, more faster over time with throughput upgrades. And they're focusing on voltage contrast, physical defects, buried defects. And also there, we do see an opportunity to come with new single beam systems, mainly for those applications that require a very high landing energy. The bigger part of the slide is about multi-beam. As I said, the system that we just discussed, the eScan 1100, I call the generation one here, already has basically a factor of 10x in terms of throughput compared to single beam systems. And as I said, we will continue to also offer throughput upgrades for those systems. But in parallel, we're already working on a so-called generation two, the eScan 2200. And there, you'll see it on the next slide, we're going to increase the amount of beams from 25 to over 2,700. And that gives us another significant step in productivity. So you will see here, we will go over 100x compared to the single beam systems. And beyond that, we actually think we can go for a different type of setup based on what we're going to do in the next step, and we call that generation three. That generation three actually will give us the throughput where we can actually have 100% wafer coverage area per hour. We'll be able to measure a full wafer within an hour using, of course, again, significantly more beams. Here we see the opportunity for multi-beam inspection. As I said, we started off with the 1100 at customers being qualified, but in parallel, working already on the system that has close to 3,000 beams. As I said, we're working on it. The technology demonstration is ongoing. I'd like to show a bit of what we have done so far, and apologize for the technical details here. What you do see here on the top, this focal plane variation, we actually have over 2,700 beams on the scintillator screen actually working, and we have been validating the through focus behavior of those beams. On the right, you see we actually have been able to validate the resolution that we need. Technology demonstration is ongoing, and we're working towards customer early access next year. Now we come to the topic of 3D integration. I think Christophe showed this slide before. We see that in all segments of the market, people will start to use wafer bonding. And of course, wafer bonding comes with certain challenges. And we think that with Holistic Lithography, we can actually tackle those challenges. Now, to give the example that has been shown before, we'll go into a bit more detail. If we look at a memory application where we started to use, let's say, one wafer with CMOS, one with the memory array that we want to bond. Now, these two wafers, they had their own life. They had their own processing, their own patterning. But now, before bonding, we have to make sure that those wafers actually match in terms of overlay. The grids should match. So that's the first part. We have to make sure that while those wafers are being processed, we know that they will be matched later on. Then we're going to bond them. So we flip one, put them on top of each other. And as mentioned before, there will be significant stress on that wafer. And that stress will be there. The only key thing is now, how do we make sure that the next layers patterned on top of that actually are aware of that and we get good overlay? Now, the first thing to do is to start measuring that wafer, trying to characterize that stress. There, typically, we need a couple of thousands of measurements per wafer because we look here at a very high-frequent overlay of distortion, nanometers over 50 nm, nanometer-wise over 50. We first characterize that wafer. Then with that knowledge, we can actually make sure that the next layer that we patterned on top of that actually has an overlay again below five nanometers by using all the actuators in the system. Once we have that, we can continue with that afterwards. It is key that we measure at the right time and translate that into corrections for our scanner, making sure that the post-bonding overlay meets customer requirements. It is not only about measurements and doing corrections. It is also about how we optimize the overall flow. This is some work we have done together with EVG and litho, where we actually started off first with a standard bonding recipe that gives, and if you look at the top part of the slide, a deformation of about 35 nm. Later, we were able to bring this back down to an overlay of below 4 nm. We looked at the process and we said, "Well, what if now we can co-optimize that bonding recipe in the bonder, being more aware of what litho can correct later on downstream?" That's what you see in the bottom. There we actually get a larger wafer deformation out. People say, "Well, that's not good." It's good if you can follow it. That's what you see on the right-hand side. So with that larger deformation present, but actually more correctable, we actually were able to drive down the overlay to about 2.5 nm. So it's not about metrology, not only about metrology, not about control, but also about making sure we understand the full flow and we optimize over the total stream. So with that, there's a challenge on wafer bonding, but we think that with Holistic Litho, we can actually capture it. And that consists of a couple of things. Having the right metrology even before bonding, the right control points before bonding, but also again, the right metrology after bonding, the control, and also be able to optimize the whole stream. And with that, I come back to the summary of my presentation. As I said, with Holistic Lithography, we're focusing on improving accuracy and pattern yield for our customers. We do it with computational lithography, supported with AI, metrology inspection and scanner optimization. And we do see challenges there in terms of front-end integration with wafer bonding. I think we have solutions for that. And as I said before, we also have seen significant progress on the multi-beam, where we are qualifying systems to be used for voltage contrast inspection in HBM later on. With that, I'd like to thank you for your attention, and I'd like to get Roger to the stage. Good afternoon, everyone, and good morning, and good evening, wherever in the world you are in the stream. It's great to be here, great to talk to you. And during the break, I heard drinking from the fire hose quite a bit. So I know there's a lot of information that has been shared with you, and I hope that's a positive because there is a lot of information to be shared. What I would like to do is to try and bring it all a little bit together for you in terms of what this means for the company, what it means for the company in terms of euros, because that's, at the end of the day, what is an important metric also for the success, I guess, of the company. So what I would like to do is talk to you a little bit about what we've done and the investments that we've made in the past couple of years, how it's actually led to success for the company, both for the customers, but also in a financial sense. And then I would like to talk about how are we looking at the future. And I think I'm going to leverage quite a bit of some of the things that particularly Christophe and Amit have been sharing with you in terms of the way the markets develop. But also I'm going to talk to you and bring back the different technology scenarios that you got from the presentation of Christophe, from Amit, but also from the different presentations from the BL leaders. So trying to bring it all together in terms of the 2,000+ scenarios that Amit was talking about. So I hope you didn't make plans for this evening because we're going to go through the 2,000+ plans, just scenarios, just to get a feel for what the size of the opportunity potentially could be. We're going to bring it together. Fear not, we're going to bring it together in three scenarios, and actually the three scenarios that Amit showed, a high growth, a moderate growth, and a low growth scenario, both from a market and from a technology perspective, and then tell you how does that pan out in terms of financials, and we're giving it away here a little bit already on the slide and also in the press release this morning that we're looking at EUR 44 billion-EUR 60 billion annual revenue by 2030 with a gross margin of 56%-60%. Numbers that sound familiar. I'll come back to that later on. Then finally, we're going to talk about capital allocation and financing. Those are the things that I would like to cover with you in the next 30 minutes. First off, let's talk a little bit about how we have created value for the company and for the shareholders in the past couple of years. I think what this slide clearly shows is that we have been creating value by really investing in technology, by really investing in innovation together with our customers, together with our suppliers, together with the entire ecosystem. If you look at this, you see that there has been a significant spike also in recent years in terms of investments. Clearly, there has been a spike in R&D. So on this slide, you see that R&D has gone up in the past couple of years, EUR 3.3 billion in 2022, EUR 4 billion in 2023, going to EUR 4.3 billion in 2024. So you really see that the roadmap, the R&D roadmap that a company has embarked on is very broad. You very much recognize that, I guess, in the individual presentations. You also see that in the recent year, we're really digesting a lot of the people that have been added in the past couple of years in the R&D department. And in that way, we are definitely driving further efficiency within R&D. You also see there's quite a bit of CapEx that has been added in recent years. So you see the CapEx in 2023 at EUR 2.2 billion, a major step up from the year before, and also a significant number still in this year. That, to a very large extent, has to do with the fact that we're building capacity. As we told you in the Investor Day in 2022, we are building the infrastructure to accommodate significant growth that a company might be faced with. Those investments are happening in these years. You also see that we've been making some focused investments in the past couple of years in M&A, particularly in those areas where we believe this was critical from a strategic perspective, either because it was critical to get a certain opportunity in the supply chain, get that recognized, or because there was a strategic opportunity like HMI. We were just looking at the story on e-beam and multi-beam because we thought it was critical for the further development of Moore's Law of the roadmap. That's why we do, those are the instances where we do M&A. Of course, there was a major acquisition of the 24.9% interest in Zeiss, given its critical nature for the business. Those are some of the investments that we've made. I think it's fair to recognize that those investments have paid off. If you look at the financial performance of the company in the past couple of years, I think it's fair to say that it's been very, very strong. We're looking at a CAGR since 2014. Let's say over a 10-year period, we're looking at a CAGR in the earnings per share of 22%, in essence, driven by three things. First off, obviously driven by growth of the company. If we look at the level in 2023, we're in fact looking at 4.5x the revenue that we had in the starting year of 2014. Very significant growth, obviously, is one key driver of the EPS. Secondly, we're looking at gross margin improvements. So you're looking here at a gross margin this year, last year of approximately 51% coming from 44% at the beginning of this period. You see there is a little, the gross margin going down a little bit from 2021 in the years thereafter. To a very large extent, that can be explained by a lot of costs that have been incurred High NA. So I think High NA makes up for more than the delta that you see there between the 53% and the 51% in High NA dilutes the gross margin by more than just that delta. So I think that's an important element to recognize in that time frame. And if you bring it all together, together with the fact that we've been doing quite some share buybacks in this period, we executed approximately EUR 20 billion of share buybacks. That gets you to indeed an earnings per share improvement of 22%. And I think it's fair to say that that is also something that has been recognized quite clearly by shareholders. So if you look at the shareholder return since the beginning of the previous decade, since 2010, you're looking at a total shareholder return of 23% in comparison to 22% for the SOX and 17% for the NASDAQ. You also recognize, and I think that is something that we all vividly see, that it went down quite a bit in the past couple of weeks. Interesting topic for conversation, I'm sure, over our dinner. It's also interesting to see that if you look at our CMDs, if you look at the previous CMD, the previous CMD that we had in 2022, you saw the same movement. Many things that you could interpret there, but just something to call out. For whatever reason, the love between the shareholders and ASML, slightly before the CMD, is somehow being tested. Let's fast forward to the future and let's look at continuing growth. I think Amit gave us how we do the model. So broadly speaking, we start with the end markets. We look at the demand for transistors coming from those end markets. We translate that into wafer demand for all the different nodes and all the different technologies that are associated with that. We translate those wafers into what is the most optimum way for the customer to produce those wafers. Which technologies are they going to deploy from a lith perspective in order to create those wafers? And then we add, and that gives you the tools that our customers need. And we add to that our assessment of the installed base business. That's in essence the way we do it. As you heard, 2,000 scenarios that Amit and I and many others needed to go through page by page. No, no, of course, you're looking at those. You're trying to assess probabilities, and that way we get to the three different scenarios that I just talked about. So this is an important slide, and I think Amit summarized it well for us. Indeed, you do notice that servers, data centers, and storage are a very significant driver of the growth. As a matter of fact, if you look at the growth between 2025 and 2030, you see there is approximately 200% growth in that category alone. So that represents more or less half of the growth in this period. So this is very significant to call out. I think Amit went into the reasons why the growth on some of the other categories might have been a little bit more muted. But I do think it's good to recognize that there is growth both in the traditional segments as well as in the category of servers, data centers, and storage, which of course is not only driven by AI. But I think it is fair to say that AI is a significant driver of the growth in that category. Also important to recognize is that if you look at the total capacity that is needed by 2030 to create the wafers that are necessary to cater to the end demand, we also look at strategic considerations. And Amit went through it, but just to recap for you, last year, or in 2022, this was a pretty significant number. You might recall that we added to the base scenario that we had at that point in time of 760K wafer starts per month. We added another 150 coming from those strategic considerations. Now we're at 85, and I think Amit shared the considerations with us. But an important element of that is, yes, we do see that this proliferation of fabs across the globe is actually happening. I think the supply security that Amit was talking about is a consideration that is important for the customers of our customers and actually is important for countries and for governments. So that's why you see CHIPS Act continuing. That's why you see this proliferation of fabs across the globe actually happening. But I think it's also fair to recognize that if we look at the foundry competition, that was one of the elements in the strategic considerations. I think it's fair to say that that foundry competition and the size of the foundry competition and what it could do to the extra capacity that could be installed is developing, but it's not manifesting itself at this stage with the vigor that people might have considered about two years ago. So those are some of the considerations why we took down the strategic number from the 150 that we had two years ago to 85 this time. Very important, and you saw this slide in several presentations, but recapping it again because it is quite essential. We do see that both in logic and in DRAM, we see over this time frame of 2025 to 2030, we see an increase in EUV exposures. And what you see here, again, to recap, and it has been mentioned in previous presentations, but this 25- 30 number that you're looking at here for logic is what we call 0.33 equivalence. So it is, in that sense, agnostic to whether it is being done High NA or it's being done Low NA, so 0.55 or 0.33. But there is a translation of a factor two. To the extent that it's done High NA, it counts for two exposures in this calculation. 25-30 in comparison to the on average 20 that we're looking at for 2025. Uptick there and potentially four to High NA layers, as has been mentioned before on the logic side. If you look at the DRAM side, I think it's also clear that we're looking at an uptick there. We're looking at seven to 10 EUV exposures there, of which potentially 2-3 could High NA. and all of that translates into an EUV litho spending CAGR in this time frame between 2025 and 2030, as you see here, of between 10%-20%. Differentiation between low and high case. And an EUV litho spending CAGR between 25 and 30 of 15%-25% when it comes to DRAM. These are important parameters that we have been using in our calculation of the financial model. Talking about the financial model, these are the model assumptions that we've been using for this model. I think it's good to go into these in a bit more detail. First off, market share assumptions are similar, I think, to the market share assumptions that we shared with you two years ago. On EUV, 100%. On ArF, we're looking at 90%. In the dry business, we're looking at 65%. Those are the assumptions that we've used in this model. What we put here into the assumptions is advanced logic, DRAM. Those are the real steam engines and NAND. Obviously, the lion's share of our business is really being driven by the advanced logic and DRAM. That's why I'm really going to focus on those two in particular. I think Amit already shared with you on the market side, he shared with you a mid case of 32%. And indeed, as you see here, we're looking at a low transistor CAGR of 28% on advanced logic and a high transistor CAGR in this time frame of 36%. So this is an important starting point in our calculation. Then from a technology perspective, the variables that we use there are, on the one hand, we're looking at what is the composition of this end market demand. And of course, the composition of the end market demand gives you, therefore, a blend of high performance, so high performance compute, and low power designs used for smartphones and what have you. We're looking High NA starting in 2026 in terms of high volume manufacturing. We're looking at 25-30 EUV exposures, of which 4-6 High NA. That is what we assumed. And again, when I talk about exposures here, once again, I talk about 0.33 equivalence. That's the way we look at that. And then if you run through that, then what the analysis tells you is that you're looking at an EUV litho spending CAGR between 25-30, as I mentioned, of between 10%-20%. Some people might recall that in the past, we had slightly different models. So in the past, we were looking at node cadences, and we were looking at spending delta node over node. We moved away from that because, quite frankly, the definition of what constitutes a node has become quite arbitrary. With all the sub-nodes that are in there, it has become a bit arbitrary. What exactly do you call a node? So that's why we moved away from that and replaced it with the data that we show on this slide for logic. If we go to DRAM, we're looking at a bit CAGR between 18%-26%. So that has gone up. You might recall in 2022, we talked about 15%-25% bit CAGR. And obviously, that is as a result of some of the things that we've been just showing because it was pretty clear, I think, from Amit's presentation that there has been quite some increase in the demand for DRAM. So that's an important element in that regard. I think Christophe showed you some interesting data points and insights into the technology side of DRAM. So in our model, we've used blends of 4F-square and 6F-square designs. And also here, we assume that there is a start of High NA in production starting somewhere in the 2026, 2027 time frame in HVM. And as we showed before, here we're looking at seven to 10 EUV exposures, of which 2-3 could be High NA. and that leads to an EUV litho spending CAGR, which is actually north of what we saw for logic between 15%-25%. And finally, the NAND statistics, as Amit showed you, NAND has actually come down quite a bit in comparison to what we were looking at last time. So also a lower bit growth here. Last time, we were looking at 25-35 as the low and the high scenario. So a decrease for NAND also in our models. But also, as you know, NAND is not a very big variable in our business. So that gives you some of the background in terms of the CAGRs that we're looking at for the system sales business, particularly on EUV, as you were just able to see. If we look at the installed base business, the installed base business in the first half of this decade, we were looking so far at a 14% CAGR of the installed base business, really driven by two things in essence. So first off, obviously, the installed base is growing, and that comes with concomitant growth in the service. Also within service, you see more and more value-based services kicking in. And then quite some upgrade business. And I think it was pretty clear to see from all the presentations of the different BLs how important this is to the BLs, how important it is to ASML, how important it is to the customers. Because extending the lifetime of the tools for us is very, very important. So making sure that our customers can continue to leverage the tools with all the upgrades that we're providing and all the services that we're putting in there to us is a very important thing to be able to offer to the customers. So that's the driver behind the 14% CAGR that you saw until today in this decade. For the remainder of this decade, we assume a 13% CAGR that has not changed in comparison to two years ago. So a 13% CAGR to, at the top line, get you to EUR 13 billion by 2030 as the high market scenario for the installed base revenue by 2030. If we model all of that in terms of revenue for EUV sales, for non-EUV sales, and for the installed base business, here you see the three different scenarios. So here you see the high scenario, so the scenario in the probability distribution, the one with the high outcome there. You have the moderate scenario in the middle, and then you have the low scenario. And what you see here is that we stopped talking about units. I know you're all very much used to units. We moved away from units. And the reason we moved away from units is because a unit in 2030 is such a radically different unit from the unit that you have in 2025 that we actually thought that that was confusing. So that's why we said we're just putting in revenue numbers here rather than talking about unit numbers because that is far more informative to talk about revenue rather than units, which, as we said, differs quite a bit in terms of what they bring. So these are the scenarios. So maybe quickly looking at what are the different drivers of it because you might look at this and say, "Hey, wait a minute, these numbers seem a little bit familiar to us," because the 44-60, we've seen that before. So I'm sure that some of you thought, "Well, the CFO has just been asking ChatGPT, 'What's the revenue for ASML in 2030?'" And ChatGPT came back with the answer 44-60, and that's what I put in. No, that's not what we did. That's not what we did. So we did it the way Amit explained. And I think what you see here is that although the revenue didn't change from an overall perspective in terms of numbers, it's still in the bracket from 44-60. It is very clear that there are quite some moving parts in the revenue that shifted it from one to the other. So if we focus on logic, net logic is actually down in comparison to where we were last year. So logic is a little lower than what we had in our models in 2022. What's the background there in comparison to 2022? So first off, the advanced nodes, as you saw in Amit's presentation, the advanced nodes are higher, so that would be a positive. But it's also fair to say that it's offset by shift in node timing. So there has been a delay in node timing, at least to some customers, and that offsets the plus that we had in the advanced node wafer demand that Amit showed in his presentation. So that's kind of a neutral in the first bullet. The second one was we discussed the 85 is substantially lower than the 150 that we talked about before. And of course, the 85 and the 150 is a blend. So it's not just all logic, and it's not all advanced, but there is definitely an advanced element in there. So that is a negative in the total logic comparison. And then finally, as Amit demonstrated, also the mainstream node wafer demand has been taken down a bit. It's still big. It's still a substantial number in terms of wafers, less so in euros as far as we are concerned, but it's still a big number of wafers because also with AI, you need all the sensors, etc., to empower it, but it is lower in comparison to what we had before. So net net, if you take all those elements together, we have logic a bit lower in comparison to the Capital Markets Day 2022. Memory has gone up. Memory has gone up for, I think, all the things that you've seen during the different presentations. So first off, the memory wafer demand was higher, primarily driven by HPC and by AI, the High Bandwidth Memory. I think the slides that Amit showed there, I think, were pretty clear. The fact that in that scenario, we're looking at an increase of 60-160K wafer starts per annum in terms of addition, I think, is an important element in the drive for that increased demand. Secondly, as Christophe showed very clearly in his presentation, there is also a shift from multi to single patterning in both from immersion multi-patterning to 0.33 single patterning and from 0.33 multi-patterning to 0.55 single patterning. That clearly is in there. That combination of things is a positive in terms of the number of layers that we see in DRAM. Then finally, the NAND wafer demand is lower, but in the grand scheme of things, that does only very little in the total memory demand. That's why we have memory up in comparison to 2022 and logic a bit down. And combined, you sort of get to the same range with 44-60. It's good to look into the details and look at your leisure. You do see that if you start with the moderate scenario, that the upside is actually a little bit more on the EUV side, and that is because we see a lot of upside, primarily also in the AI space. So that's where you see the upside. And the downside, I think, is a little bit more distributed over the different technologies. My favorite topic, the gross margin. The gross margin development that we have here. So the gross margin, if we take the midpoint of the gross margin in 2025, and I told you a significant element in the negative development in the past couple of years in the gross margin has been all the cost that has been taken into the P&L to High NA up and running. So we have a starting the midpoint of 52% as the starting point. And you see that the lion's share of the improvement to get you to the midpoint of the gross margin of 58% is actually in EUV. Now, what is that? It's a combination. First off, obviously, Low NA, where we continue to see you saw the roadmap. We continue to quite a bit improve the throughput. Higher throughput, as you know, comes with higher ASP and ultimately comes with good improvement in the gross margin. So that's an important one. Second volume, more volume in 0.33, and because at this stage, 0.33 with the gross margin improvements is really contributing to the corporate gross margin rather than being dilutive, as it was in the past, more volume in 0.33 actually helps in driving up the gross margin, so that's a positive. Those two are positive. High NA, you will, of course, see a sustained increase in the gross margin, and we do believe that by the end of this decade, it's not entirely at the level of the corporate gross margin, but it's very, very close. That's the way we model it today, and as a result of that improvement, it's going to be significantly less dilutive to the gross margin than it has been in the past couple of years, even though the number High NA systems is going up, so that's the EUV story. And if you take that all combined, that gets you at the midpoint 4%. Then we have a non-EUV. We have a 1% improvement in the gross margin. That's volume to a large extent, a little bit offset by mixed effects, a bit more dry in comparison to immersion, but net still a 1% improvement there. And as you know, we continue to improve our gross margin on the installed base business. And a very important element in there is the service business. We have been very successful, I think, in the past couple of years in driving up the gross margin on service. And doing that on all parts of the business, we do believe that 1% further improvement at the corporate level coming from the installed base business is achievable. So that gets you to the 58% as a midpoint for the gross margin by 2030. How does it all end up then in the financial model? The financial model is more or less in line with the financial model that we presented two years ago. I'm going to call out three deltas. The three deltas in this model. It starts with SG&A. We have SG&A a little bit higher than we had it two years ago. 1.7-1.9 is what we have in here. A very important part of that element is the community engagement that we perform. You saw the slide that Christophe had on that front. As you know, with all the growth that ASML is experiencing here in this part of the world, in this part of the country, there is a lot that needs to happen here. There is a lot of infrastructural development that needs to be done in this region. People close to the region know that. The housing, the infrastructure, the public infrastructure, schools, etc., a lot needs to be done. The Dutch government has put forward a significant package to help the industry grow, so that has been very positive, but there is an element of co-financing in there, part of that finds its way into the SG&A, so that's, I would say, the most significant driver up of SG&A. Second element you see in there is CapEx, so CapEx at 2.5, quite a bit higher than what we had two years ago, and that is related to the high productivity platform that we talked about. You don't get the revenue and the profit of that yet in 2030 because, as we showed, the high productivity platform is actually only going to kick in in the early years, if you like, of the next decade. But at this stage, we're definitely building because there is a lot of adaptation that needs to happen. And that finds its way into the prediction of the 2.5 here by 2030. And then finally, a small one, the effective tax rate is a little bit up as a result of our current understanding of some of the tax laws across the globe that are effective for us. A few words on flexibility because with the huge window that we still have from EUR 44 billion-EUR 60 billion, flexibility obviously is important. What you see here is that the flexibility is there to a certain extent on the headcount. You see it on the left-hand side. And definitely also on the R&D side, there is flexibility. But the big flexibility that the company enjoys obviously is in our operating model, where if you look at the cost of goods of the tools that we ship, only 13% of that is labor. 87% of that is what comes from suppliers. So that's a very significant part. And obviously, that gives us an innate flexibility in our operating model, which I think is important. Finally, shareholder value creation. A couple of things. In essence, confirming the capital allocation, as you've heard us talk about that before. So what comes first is that with the cash that we generate, we use that to make all the investments into the business that are critical. So the investments to execute our long-term roadmap. So this is CapEx. This is R&D. This is the support of Zeiss in making some investments and loans to Zeiss in that regard. So that's critical. That goes first. And then whatever is left is obviously returned to shareholders, sustainable dividends per share that will grow over time, as you would have seen us execute on in the past couple of years, paid on a quarterly basis. And whatever remains as excess cash is being distributed back by means of share buybacks. And on the financing side, you would have seen us in the past couple of years increasingly maintaining a significant amount of liquidity to ensure continued business operations, whatever the circumstances are, and maintain a capital structure that targets a solid investment-grade credit rating that we currently have at A2 and A+. Our approach to capital allocation in that way has not changed. And as you see here, focused investments, we've gone through that before. And the cash returns that we've been able to do to shareholders cumulative over this period, a little under EUR 40 billion is what we've been able to distribute in terms of dividends and in terms of share buybacks. And dear friends, that concludes my presentation. Thank you very much for your attention. And now I would like to welcome Christophe back for some closing remarks. Thank you very much, Roger, for oops, we get something back. So first, I'd like to thank you for your patience and attention. I was looking at the page number, and we just passed 200 pages. So I think we all realize that this is a lot to take for you. But our intention with that is to inform you as much as we can. And I told you before, we did spend quite some time to prepare this day. We thought this was a very important day. We thought it's very important to share with you our view of the future. I think we have been enjoying a great relationship with you for many, many years. And I think we want to continue to really do our very best to share with you at any point of time, basically, where we believe the markets stand, where technologies stand, and of course, where we stand. So thanks for being patient. Thanks for going through all those explanations. And I hope that they will be useful for you moving forward. And we have many, many more months, most probably together with our IR team to discuss and answer more questions. So that's the first thing. The second thing, since we gave you so much information, we thought it's a good idea to summarize it a bit again. I will go through some of the key discussions we had. I will start a bit with the strategic view. Roger will come back one more time also on the numbers. The market, the semiconductor industry, and the stance we believe is going to remain strong because semiconductors are going to be needed for any great invention moving forward, and also because AI is going, if anything, to add basically to that demand. So we see still a very, very resilient market. I think a lot of our peers, a lot of our partners in industry are giving the same message. I sometimes say the market with AI is better than the market without AI. So I would say the market view we have in 2024 is most probably even better than the one we had in 2022. This being said, AI will take some time. So we're still not sure exactly how this will play out, how it will be adopted. So I think we have to see how this evolves next year, the year after, and how this happens, basically. We also talked about the market size being the same as two years ago, EUR 1 trillion, no change. But I think one of the key takeaways I hope for you from this discussion is that the mix itself is very different. And this has some impact on what our customer will do and, of course, how we are going to serve them. More advanced logic, more DRAM. I should call it advanced DRAM today has always been good for lithography. It has always been good for ASML. And I think you have seen also through the video of Dr. Cha t hat we are already deeply engaged with our customer, basically, to work with them and address those next challenges. So that's the first thing. The second thing, we talked a lot about technology because innovations will be very, very important moving forward. It has always been. We talked about Moore's Law in the past. I show you today that Moore's Law is getting a bit on steroids with AI. And we need basically to continue as an industry to provide more and more solutions so that the cost, so the energy consumption of AI basically stays where it should be so that this can really happen. So there will be a lot of innovation. And in our case, we believe that lithography will remain at the heart of our customer innovation. And we talked a lot about advanced logic, DRAM. I could repeat. I think Herman showed you also that even on mainstream semiconductor, in fact, the number of DUV layers is also increasing. So even there, we spend a bit less time. But we still see that lithography is still a very, very good way to drive innovation, to drive costs down, to drive down energy efficiency. So we are going to continue to innovate on our portfolio. EUV, I like to say it because getting to 200 W for ASML has been such a difficult mission. I mean, we have been sweating for years. We have been talking to you for years without showing any progress on power. And today, we can proudly stand here and say, well, we know how to get the power up for many, many years. Not only we know how to get the power up, but we know how to reduce the need for power because we're going to move to optics, which is coming to with High NA, which allows us to reduce the number of mirrors and therefore give us back a lot of productivity. So we have in hand a technology that will allow us to extend EUV. I would say at least for the next 15 years, reducing costs, reducing energy consumption. We will pace, of course, innovation. We will introduce Hyper NA when the time comes. We will work on productivity. But all of that gives us a way to really help our customer. Like I said, we can commit to our customers to reduce the cost of EUV exposure, not because we are going to give away our profitability. I think you saw that with Roger, but because we can, because we know how to do it. And that's a luxury. And that's something that is very important. So what's next after EUV is a question that we get a lot. The answer is simple. It's EUV. And it's EUV for the next 15 years. And this is the value of this technology. And this is why also the investment we have made on and High NA, i would say, has been such a very smart investment. Then there is Holistic Lithography. So I know it's always a bit of a complicated topic for all of you because this brings many, many different pieces together. You have a lot of different metrology. You have a lot of different models. We have a lot of different correction. But there, I will say, because of the accuracy, our customers are going to look for the demand for control of the process, which is going to be even higher after bonding because bonding is doing a very bad thing to the wafer, practically. And we have to go and repair that with process control. So the demand for control, and therefore the demand for metrology, and therefore the demand for a very smart model that Marco started to call AI because AI is going to be part of that. AI is also an opportunity for ASML. This combination is still great for our customer. And the value Holistic Lithography has generated in the past is enormous. If we had to deliver the accuracy today, we have delivered with our Holistic Lithography. Without Holistic Lithography, just using the scanner, the cost of a scanner will be enormous. Holistic Lithography has allowed us also to keep lithography affordable for our customer. And this will continue to be the case. And finally, DUV. So you also saw from Herman that this is a very important product, very, very important product. It's not all about EUV. EUV is doing the critical stuff. But then you have to do all the rest. And the rest is also expensive. So you also have to work on costs. You also have to improve those technologies. And I think what Herman has shown you is that we are still very creative on the technology. We're improving performance, productivity. But we're also looking at any possible ways to reduce cost with our supplier. You saw the example of the boat shipment. The boat shipment is a bit an example for us on how far we are willing to change to address those new challenges. I can tell you that talking about shipping a tool by boat five years ago in ASML was seen as a crime. But we are also capable to change in the way we run operations because this is becoming more and more important for our customer. Finally, installed base. So the good things with installed base is, of course, the number of tools goes up over time. And the ratio between the number of tools you ship every year and the number of tools you have on the ground is always going towards the number of tools you have on the ground. We've done quite some work with our customer to demonstrate the value of our service. There was a time where, in fact, on DUV tools, service was coming for free in ASML. I think you've seen with Herman that this has changed quite a bit, and basically, we continue to do that because our customer can use those systems for 20 years. When they look at the cost of lithography, they depreciate the tool over five years. Well, in fact, they could depreciate the value of the tool over 20, maybe 25 years, so this is also very important, and finally, ESG. So Roger said it. We are even willing to increase part of our SG&A in it to contribute positively to the community. We believe this is part of our responsibility moving forward in ASML. That's for the big picture on the strategy. Roger will give you back one more time the EUR 44-EUR 60 billion range, and the backlog is robust. Absolutely. Thanks, Christophe, and very much in line, so starting point again, end markets. End markets as a total number, not different, not dramatically different from what we had two years ago. Composition definitely different, and the composition also more to the advanced side, advanced DRAM, and advanced logic, so that's a positive. We've become a bit more conservative, however, on the strategic side, so the 150, we brought back to 85. So that's prudence that we applied in light of the considerations that we gave before. Yes, the proliferation of fabs across the globe is happening, but also the progress that we see on the foundry competition, while it's there, is maybe not as exacerbated as some people might have expected two years ago, so that's why we've been more conservative in that part. Combination of those two means that on the market side, on the logic, we take it a little bit down. On memory, we take it a little bit up because of the spike in DRAM. On the technology front, I think what we've been able to demonstrate, I think, in this presentation is that we're making really good progress on all parts of our business. I think when it comes to logic, I think that is more or less in line with the expectations that we gave in 2022. I think for DRAM, I think our comfort levels have actually gone up quite a bit, and the comfort level there that we have in terms of being able to get more and more layers on EUV, that confidence level has gone up based on the presentation that Christophe has shared with you. And the combination of those two is that we're looking at a larger memory business and a slightly lower logic business. So not still the 44%-60%, but again, there with a different composition. And based on the potential that we see to improve the productivity and the value of our tools to the customer, the value that we bring in our installed base to the customer, and our ability to control cost, I think that has also given us good comfort that even though we're starting in 2025 with a lower starting point as it comes to the gross margin, that we're still able to improve and still believe that the window of 56%-60% with the 58% as a midpoint, that we have a clear path and clear plans towards that. I think that is it, Christophe. And I guess with that. Time for Q&A. Time for Q&A. Yeah. Thank you, guys. OK, let's jump into bringing the presenters up here. We're going to bring the chairs up. I'll take that. And we'll get the chairs moved. Yes, please. And we'll also have, for those on the webcast, we have a large number of questions coming in. So we'll be working through those as well. So give us a few seconds here. We'll get things set up. Good. Thank you. All right. So let's get started. Oh, the microphone's coming here. Thank you, Didier Scemama, Bank of America Securities. Thank you for all this information. A lot to take in. A couple of questions. So you say you're bullish on AI, but I would argue you're bearish on AI for two reasons. A, when you look at your CAGR for smartphone and for PCs, it's actually quite low. So am I correct in assuming you're assuming effectively no replacement cycle driven by AI, number one? And on the data center opportunity, you're talking $350 million or billion dollars. Apologies. I think AMD have talked about EUR 500 billion in 2028. So I guess my question to begin with is, if we were to be a bit more optimistic on edge AI and on what AMD are saying, are we tracking closer to the EUR 60 billion? That's my first question. The second question is, a lot of focus today on cost, productivity, and just making EUV more affordable effectively and greater reason for customers to upgrade. I wonder, as the industry transitions to chiplets, whether that benefit is somewhat negated, or do you think actually EUV is enhanced or complemented by chiplets? Thank you. I'll take the first. You want to switch order? You'll go first. I'll take the first, and Christophe takes the second. So, Didier, thanks for your question. I think when it comes to data centers, I think Christophe showed it in his presentation. The potential is huge, and you showed it in your presentation. The potential of AI is huge. But there are also obstacles that need to be overcome. That's why we took a view that some might look at as prudent. That's the view that we took into our base case. To the extent that the opportunity that all the roadblocks are being removed and you get to a higher number, as Christophe said, be my guest, put it into the model, and off you go. When it comes to edge AI, again, there's a debate. I think we are of the view that it might take a bit longer before edge AI really powers the existing devices in such a way that it's going to be absolutely compelling for customers to replace their devices earlier. So again, you might argue we've taken a bit of a prudent view there. Most industry analysts that we see believe this will definitely come, but they're hesitant to confirm that that's already there by 2030. So that's why we've taken a fairly prudent stance to the extent that this is going to manifest itself. And you're absolutely right. And you're going to see larger chips there. Yeah. And on the second question, I think the short answer is no. So I don't see that there will be some potential value taken away because chiplets are being used. I think this is being used extensively today. It's a way to optimize already the cost. I think that explains also the mainstream part of the semiconductor, which, remember, we still believe is a large part of our business. So the idea there is that if you can have a functionality using a lower node, either for logic or DRAM, I think you should do it. I think that trend will continue. AI or the need for high-performance logic, high-performance DRAM, I believe, on the other hand, will in fact increase front-end integration. So today, you talk a lot about advanced packaging to create more density. I think we will see more integration in the process itself. So that's a dynamic we have to watch as well. We don't know exactly how it's going to play. But I think the trend is towards a lot more integration on the wafer itself. So you have those stories about chiplets. You also have those stories about full wafer chips that are already developed by some of the AI customers. I think TSMC has been talking about those products also publicly a few times. All right. Thanks. Start here. Thank you. It's Mehdi Hosseini, Susquehanna International. Two questions for Christophe and the team and one for Roger. Can you help me understand what's going to drive the increased system commonality between Low NA and High NA? you had a reference going from 50% to 98%. And just I don't want to get into the engineering aspect, but what are the key parts of that increased commonality? And number two, it seems to me that Holistic Lithography is an enabler for selling more expensive EUV tools. Maybe you can just debate me on that. And then for Roger, given the fact that you're more conservative near term 2025, would the buyback be more of a year from now? Because I think that's the big difference between today and Capital Markets Day in 2022. If I'm not mistaken, I think back then, 2023 proved to be a stronger year, and your cash flows improved. And I think you had a stronger buyback. And is that the one key difference today versus the last Capital Markets Day? OK. So I would try also to be simple on your first two questions. So if you look at the commonality moving forward, what you envision between Low NA and High NA is to try to have the optic being the only difference. That's the idea. So everything else except for the optic will be about the same. The source, of course, the stages, but we even go down to the frame, so that's the leading principle, and that principle will be optimized, of course, based on the cost of the two platforms, but if you start from the idea that everything is the same except for the optic, and if you look at the bill of material of the tool today, you come to this number. It's far above 90%, so that's the simple answer. Now, the question about Holistic Lithography, there's always the question about cost, which sometimes could mean the cost for the customer or the price of the tool, and I try to touch both, so like I said before, the reason why we do Holistic Lithography is to reduce the cost of an exposure for our customer. I took the example of overlay. With Holistic Lithography, the cost of overlay is a lot cheaper for our customer than it would be if we didn't have Holistic Lithography. So when it comes to our customer, the cost of litho-exposure using Holistic Lithography is going to go down versus not using it. Now, for us, of course, the product Marco was talking about are coming on top of our scanner and generate value for ASML. But that's a bit the win-win situation we've been trying to create forever. That's also the win-win situation I've been trying to explain around the improvement on EUV cost of exposure. We will reduce the cost for our customer, and that will translate for us into more revenue and more profitability. This is the simple model. So if one day you don't get bought, most probably one party will say, this doesn't make sense. As long as we get booked, everyone is happy. As to your question on share buyback and liquidity, I think in 2022, it was clear that order intake was very, very strong at that stage. We were coming out of a period, I think, where we were very much supply constrained, and being supply constrained meant that customers, even though the downturn was starting to manifest itself, still customers were very bullish in placing orders, and as a result of that, providing us with cash. I think what we've seen last year in particular is that that has kind of cooled off. I think the reason for it cooling off is, well, first, our customers know that we have been building capacity, so to be supply constrained is not going to kick in as rapidly, and frankly, some of our customers have gone through some very tough days. And there we also believe that it was appropriate for us to help them by giving them extended payment terms also for down payments and what have you. So that has happened. And I think that has led indeed to, at least for the first quarters of this year, to a lower cash inflow. We've also taken quite some inventory High NA, taken quite some inventory for further ramp Low NA. so as a result of that, I think indeed the free cash flow hasn't been as strong as it has been in previous periods. I think realistically, even though we're not going to give any guidance on share buyback, we never did that and won't do it. But I think realistically, if the market comes back, that will also come with healthy order intake as a result of that healthy down payments and a healthy building down of the inventory levels, as a result of which the free cash flow should get again to good levels. And that would allow us again to perform share buybacks. If that is the big difference with the Capital Market day in 2022, I hope not. Right? Because this is a bit of a short-term thing that, as a result of the cycles that you have in the industry and the way we try to help our customers and try to help our supply chain, that could lead to a situation where sometimes our cash flow is a little bit under pressure. But as I've also shown, we have a capital structure. We have a liquidity structure that allows us to play that role. So from that vantage point, I wouldn't see that as a major difference. I think the major difference, if I may express that on your behalf, the major difference is, A, the way we look at the market and the way AI has kind of redefined the market to a certain extent. And I think the very strong progress that we're giving on the development of our technology, I think those, to me, would be the key things that I would highlight from the meeting. Aside maybe over here. Sandeep. Hi. Sandeep Deshpande, JP Morgan. Two questions, if I may. Firstly, on your growth assumptions in the memory market, clearly, I mean, you're more bullish on the DRAM side. You do seem a little more bullish than what the DRAM makers are saying. Is there a reason from what they are ordering to you, which is why you are more bullish on bit growth and then particularly in DRAM? And then my second question is regarding the competition in the industry. I mean, there is this worry that overall competition is declining and that the number of customers that you will have in the long term will not be as many as you have, or at least substantially. And is that having an impact in your negotiation on pricing at all on the tools, particularly from the most healthy ones of your customers because they are so critical to your growth in future years? I think, Sandeep, on your first question, and Amit, please weigh in. But obviously, I think what you're hearing from our customers, I think, is a little bit more short-termist. I think what we're looking at is the longer-term demand, and I think, as Amit has been demonstrating, the longer-term demand, given the dynamics in the end markets that we showed, the longer-term demand on the advanced DDR, on High Bandwidth Memory, those dynamics are very, very positive, so that's the reason why, indeed, particularly on that front, you do see a very healthy development and a kicker over that five-year time frame, healthy as we've portrayed it, so is this completely synced up with customers, well, the longer-term ideas and the technological dynamics are, right, because obviously, we are in very close contact with our customers on the technology that they are deploying, but I think the delta that you might observe is really the time horizon, we're looking out all the way to 2030, and I think the commentary that you see is a little bit more short-termist. If I may just complement, we just saw it in the room right now. Didier suggested that we are being too conservative. On the back of that conservatism, the resultant DRAM demand to you looks more bullish compared to what our customers are saying. That's exactly the dynamic we look in front of us. There's a range of possibilities. To Roger's point, we are giving greater weightage to the end markets. At the same time, we acknowledge the enablers, but also the inhibitors at this nascent stage. Putting it all together, indeed, we do think our view is fairly constructive on the long term. Yes, we did look at what our customers are saying. We do believe it's good to be constructive on the long term. I'm saying be constructive, not go sky-high bullish, not go pessimistic. And maybe the second one then, Christophe, on that. Yeah, the second question is a bit of a more difficult one because, of course, there's a lot of things happening on the short term. So I think that triggered this question. I'll split the answer into two. So if you look at memory, I think that clearly there were some early winners on the High Bandwidth Memory. And this had to do with, I would say, the advancement those winners had in their R&D product versus other. I would be surprised if over time, I would say the key DRAM customers are not all playing in this field because the demand is such to Amit's point that most probably the market is going to need to see that happen. So that's for memory. So I think some maybe short-term turbulences. But on the long term, I think most probably we go back to the scheme we know. For logic, advanced logic, of course, you have one formidable company that for many, many years have been driving foundries, and they have been always ahead. I think this is true, by the way, for many, many years. If you look at the market share in foundry, this has always been skewed towards one of our customers. I think it's still true today. A lot of discussion because we had a lot of questions about how many players there may or may not be. I'll let you guess yourself. But if you look at still geopolitics, if you look at the overall demand, including over time a higher demand for logic in DRAM, I think that's something also that will come. I think that this will take a lot more time to answer the question you're trying to answer. I still think that in the long term, we will see everyone fighting for this business. That's my assessment at least today. Maybe just a couple from the online. I think the one that seems to have the most to do, there are some questions about 2025. We gave some update last quarter. We're now talking long term. Can we say anything about the midterm? We want all the blanks filled in. Yeah. Yeah, sure. Yeah, sure. We've given an update on 2025. We give an update six years ahead of 2030. I think that's good enough, and people can obviously look at 2025, look at where we want to land in 2030, and then ask themselves the question, is all of that going to happen in 2030? In all likelihood, not, right, but we set 2026. We look at 2026 as a growth year, and I think people should just look at what we set for 2025, look at 2030, recognize we look at 2026 as a growth year, take it from there. Yeah. Another one was with all the discussion on the way the roadmap's evolving with the 3D possibilities there. It looks like there's a lot going on within Holistic Litho space that Marco identified. Is that something that we see as a space that we fill, or is there something that we're looking to do, any acquisitions or anything around that arena? Well, in general, I think if you look at our plan, our plan does not include any acquisition, right? So our plan, there is no M&A in there, and we've talked about this before. The opportunity that we see without any acquisition is huge, right? If we look at the opportunity that we have ahead, it is colossal, and that's why we don't have it in the plan. Does that mean that we're going to categorically say no to any acquisition? No, that's also not the case, and you've seen that before. If we see that there is something that we think is critical for us to adapt because it's critical on the roadmap of our customers, and we need to do it, then we jump in, right, and that's what we've done, for instance, with HMI. That's what we've done in constraints on our roadmap, but at this stage, we didn't plan for it. It's not in our plans, and we think that the opportunity that we have for the business that we're currently in is massive. Yeah, if I can add to that, I think I hope we demonstrated today we have a lot to do in ASML. And I think we continue to be very, very focused on the execution of our strategy on EUV, on D UV. And on Holistic Lithography, if you recall what Marco, what I was presenting, I think Herman touched on it a bit, this is still very much about what we can do today. So we've been talking about scanner control, which we have. We've been talking about metrology, which we have. So this is built basically on some of the things that are already in-house. So the focus is always on getting that major strategy going because this is really the biggest part forever of what we are going to do. And if you look at history, you're right, all acquisition has been always about maybe taking something that maybe would not have worked if it was in-house. And I think that logic will continue, right? So we stay very, very focused on our strategy execution. And if on the way we feel that one element may block us in doing that, then we will consider that. The same logic, I think, apply moving forward. All right. Thanks. C.J. Thank you. CJ Muse with Cantor Fitzgerald, and thank you for hosting us today. Two questions High NA the first one, you talked about HVM in 2026, 2027. Curious if you could speak to layer counts and the breadth of customer adoption across both logic and DRAM. And then a longer-term question High NA in terms of possibly increasing the size of the reticle. Obviously, that would be enormously disruptive to the mask guys, and you would need to have TSMC behind it. But you have companies like NVIDIA who are reticle limit, and that could be a way to drive improvements, particularly in the AI space. So we'd love to hear your thoughts on that. Yeah, so I'll try to answer. Maybe Peter, feel free to add. So on the question on the high volume manufacturing, I think it will be both. So I think the adoption in DRAM logic we see happening around the same time. As it happened before Low NA, most probably logic and DRAM customer will be looking at using High NA for one or two layers so that they develop their understanding of the technology, they learn about it, they develop whatever they have to do in the factory, and then they will basically scale up, which is pretty much the number we were showing for 2030. So we always look at what we call a two-nodes adoption. The first node is just to almost kick the tire, if you want, and then you get really serious on the next one. So I think this will happen around the same time for logic and DRAM. It's always difficult to point to who will really go first, but it won't be a huge difference in terms of timing. On your question on the mask, I think you said it yourself. This is indeed a major disruption. I think we have explained to our customers we can do it. We know how to do that. It's something we could do within a few years in ASML. A larger mask is not a bad idea for lithography because you can scan longer. It was a bit the story of Elon from xAI. We like, in general, bigger masks, but we cannot do it with the entire ecosystem. For the entire ecosystem to move, I think the voice of our customer is more important than ours. I think we have already one customer very vocal on that. I think you mentioned the one that at some point of time has to be convinced that this makes sense, and then the industry could move. So there, I mean, the value is such that I will say as a customer gets used to INA, they see the value, they like it, they have it in high-volume manufacturing. I think this will be a natural discussion. And that's why we're not shying away to have the discussion with our customer and the ecosystem. And maybe while since we're on that topic, Peter, there's a few questions here on the stitching and use of INA and why we're okay that customers are okay with the use of stitching. And maybe just a quick explanation on how the half-field works in terms of the final productivity, meaning the specifications you put up there, I assume that includes the half-field, those type of questions. Yeah, so when you expose half-fields compared to full fields, you have to expose more fields on a wafer to get to the same coverage. Of course, in the way we have designed the tool, we took account of that. And we have increased the acceleration potential of our stages to be faster, to move faster from field to field to composite for the half-field. Now, indeed, as I explained, once you have a larger die than the half-field, you have to stitch. The intrinsic control in the system in terms of overlay and imaging control and the way we can compensate for that also with our knowledge on how to do the mask and how to stitch masks, we already showed that this is an engineering problem. And an engineering problem results in a development cycle that you can implement in high volume. So there is no significant concern around stitching. Right. Thank you. Andrew. Thank you. Andrew Gardiner from Citi. Just a first follow-up from C.J.'s High NA insertion. If we're thinking of that in the 2026, 2027 timeframe and sort of the customer interest there for one to two layers, you've got some in your backlog today. My math sort of mid-single digit billions of backlog for 2026 and beyond. I presume most of that High NA. is that enough to see customers sort of draw down that backlog to get that insertion done, or will we need to see additional orders High NA on those initial nodes? And if so, what are your lead times? When would you expect to see those orders come in? Well, I think the number you mentioned is a big number, by the way. And I think that is also important for our customer to, I would say, to get the return on those major investments because, as know, High NA is a major investment. So those tools will definitely support the initial insertion, right? And that's why we got some of those orders before. Not fully. So it means that as time goes, we will see some addition. But the next, I will say, major wave of order should come for the bigger node because this is where you're going to look at a much higher volume of machine. That's also when we will be looking at ramping our production a bit more. And that higher number of machine, we have always given 2027 as a starting point. So that will be out of the two nodes insertion I was talking about, that will be the second one. I think the first node with some addition could most probably be started with some of the tools we have in the backlog. Okay. Thank you. And also related to that, the sort of four to six layer count on advanced logic by 2030, if you don't have the slides up, but if I sort of remember, if we double that to get to a 0.33 equivalent, you're almost implying little change in terms Low NA layer count as we look out through the subsequent node transitions. Is that right? Is there cannibalization happening? So how are the customers developing their process around that? So we talked about Low NA EUV layers because as we move in the roadmap, some layers require EUV. And yes, some of those layers may to High NA. and by the way, they move usually as a factor of one to two because you go from double exposed to single exposed. So that's why we look first at the total picture. And then you get some cannibalization, of course. But because you keep moving to the right, you also get some Low NA layers. So that's a bit more tricky. Mostly, it's a good question for follow-up. But we first look at the total potential Low NA EUV equivalent, and then we try to decide how this would be allocated between one or the other tool. That's for the capacity, so that's something important for us. If you look at the revenue, I will say the allocation matters a bit less. That's also why we try to not confuse you too much with all those numbers because at the end of the day, the change is minimum. But if you look at the math, Andrew, I think you're pretty close to it, right? So we set 25-30 tools. And we set High NA exposures. Sorry, exposures, Sorry, exposures, 0.33 equivalent. So what that means is if you take the highest point of that, so if you take the 30, you take the six layers, that gets you to Low NA and High NA layers exposures. I mean, that's what you would end up having in that model. Does that make sense? Thanks. Right behind, Janardan. Hi, it's Janardan Menon from Jefferies. Just to follow on Andrew's question on the capacity side. So you've so far talked about Low NA and about High NA. but what you're describing here seems to be a situation where you'll probably end up by 2030 with more than Low NA and probably well below High NA, depending on how the additional wave of volume translates to High NA, to Low NA. so is your 90, is that a fungible number? Can you change the capacity, or does this mean that you have to add new capacity on High NA side if that were to be the situation? And then just at the other side of that revenue equation, you've sort of indicated in the past that every time you add a wafer throughput on Low NA machine, the ASP sort of rises by in the region of EUR 1 million. You've talked about as much as 450 wph on some of Low NA machines. I thought I saw on one of the slides. So does that broad thumb rule last all the way to that kind of wafer throughput? Is that what we're looking at? And should that be also the same on High NA machines where also you're indicating pretty high throughput in coming years? And is that how we square the revenue calculation? And just a last quick one for Herman, perhaps, which is on the rising layer count on DUV. I'm just wondering where does that come from? Is it because if you go to a 1.4 nm, yes, your EUV layer is probably flat or rising as the calculation showed, sorry. But is the DUV, does the immersion layers rise at that point, or is it coming from 28 nm, 20 nm? Where's that coming from? And especially given the context of what you're saying Low NA is replacing double patterning on immersion, where does that rising, I mean, DUV layer count come from? Thanks. Yeah, I can start with the end of the question. So what you see in the roadmap is a lot of changes in the architecture of the different devices for logic, for DRAM, for NAND even. Every time you change the architecture, so we talk always about the number of EUV layers, but I'll give you an example that you well know. If logic move to Gate-All-Around, this requires some more lithography. But those lithography exposure will be done with DUV. They won't be done with EUV because they're not critical. I'll give you another example. If a NAND customer decides to make more tiers, that again requires more lithography. We've seen the lithography number of layers for NAND going up over time. Again, that's not EUV at all in this case. That's most probably KrF. Every time you have a change in architecture, this requires more process steps. Those process steps that are not lithocritical will be done with DUV. That's why you still see the number of DUV increasing. That's true for NAND, logic, and DRAM, to be honest. We spend usually less time on that. That's why we made a choice to show it to you today. That's still quite significant. This has been happening also for many, many years. When it comes to the question of the mix in EUV and what that means ultimately for capacity, as it comes to capacity, your question is one of the key reasons why indeed we're looking at common platform, right? Because at the end of the day, we want to give customers as much flexibility as they can in order to optimize the tool mix and also the EUV tool mix for themselves, right? That's why the common platform, which also means that building those platforms can in essence happen in the same environment, in the same type of cabins, is so important to us. So that's what we're working towards. In terms of capacity, we have been working, as you know, in the past couple of years on creating sufficient capacity both for DUV and also Low NA. so I think we have good flexibility there to the extent that we need more capacity High NA, and that might be the case. We'll definitely have the opportunity to build capacity there, but we will do it in such a way that that capacity can then also be used through the common platform, right? So that's the decision that we need to take. We still have a bit of time there in order to see how customers are deciding on the exact composition. So we have time to do that. But I think we do have the flexibility in our model to accommodate that. Financially, you're quite right. In terms of revenue, it doesn't really matter a lot, right? So from a financial perspective, whether they take High NA tool or Low NA tools doesn't have a huge implication for our financial model. In terms of the pricing on the high productivity tool, holy cow, to start negotiations with the customers on a tool that we're going to sell eight years from now is probably not what we should do and definitely not in this meeting. I think in the past couple of years, I think we have been able to get a shared model with customers where we share the value of the tool, the incremental value of the tool with the custome r in a fair way. And that has not led to a very strong correlation between the throughput improvement, only one of the improvements, because we give more value to the customer than just throughput improvement. But it's led to a very strong correlation between the throughput improvement and the ASP. We think that we can continue to deliver value. We think the value sharing model will continue to happen. But exactly how that's going to pan out and whether the high productivity platform is going to give you the same linearity, that's a bit too early to comment on. Thanks a lot, François-Xavier Bouvignies from UBS. I have a quick question on the layer count you described for logic. If I remember, 2022, you said you expected 20- 30 exposures for advanced logic. And now you are targeting the high end, 25- 30 for the end of the decade. Now, the chart that you showed the most is the imec chart about the nodes and the improvements. And when you look at the metal pitch size, the 18 nm pitch size was supposed to be in 2026 at A14 in 2022. And now it's in 2029, 2030 for A10. So you had the kind of a move on the metal pitch since 2022. So what is driving your confidence that you're going to get to higher end of the exposures when the roadmap of the pitch seems to go to the right? And also in the context of Christophe, you said that it's slowing down. And we know that your customers are doing a lot of improvement in terms of the layers as well, always to get more out of their exposures. So first, I'll first clarify the numbers, and then I think Christophe can take the specific roadmap question. So just to clarify the numbers, the 20- 30 referred to the 2025 and 2030 period. So the 20- 30 was for the period of 2025- 2030. So that was not linked specifically to 20- 30 to the year 2030. So you should not interpret the 2025-20 30 by 2030 as an increase, right? The 20- 30 was related to the 2025- 2030 period. So just to clarify that. And by the way, we also recognized when I gave the overview of the pluses and minuses, we also recognized there the slippage in timing in node cadence. So that is consistent with the comment that you make. Yeah, and on the second part, so I think first we look at the five years horizon, which means that we have a pretty good understanding of where the roadmap of our customer goes in those five years. If we were to look five years beyond, it's a bit more complicated. So that's the first part. So I think the confidence we have on the number is also based on the fact that the level of discussion we have on this period of time is quite detailed. The second one, you're right to refer to` imec roadmap. I think that's what I tried to explain a bit during the presentation. So for a long time, I think the advanced logic roadmap was driven by mobile application. When mobile application was driving the roadmap, the justification to move fast to the next node was very difficult because the need for high power computing was not there. The need for low power consumption was there. There was a bit of a different demand than what you see today where AI customers are, I would say, de facto now driving advanced logic. Their appetite for advanced node is pretty high. If you look at two nanometer node, if you look who are going to be the first customer buying from two nanometer, those are the AI customer. The mobile customer will come a bit later. There's been a bit of a changing of the guard, if you want, on who is demanding the most advanced application today in advanced logic. And that, I think, will create a dynamic that could a bit revert, but now I'm speculating. But you ask a technical question, so I give a technical answer. You could see basically the trend reverting a bit because mobile was kind of saying, well, yeah, it's okay, it can wait. AI is saying, no, I want it earlier because if not, my cost goes like this and my energy consumption goes like that. So that's the dynamic we see. We talked about trend today. That's a trend we see. But like a lot of the trend, they have not fully played out in the market. But that's what I would call a positive trend. So AI driving advanced logic, if it remains like that, will result in a much more aggressive roadmap in logic than when mobile was driving advanced logic. That's the bottom line. Very clear. Thank you. My follow-up question is on High NA for memory specifically. To what extent 4F-square might impact the insertion? I mean, do you think they would do both at the same time? Or if they decide to go for 4F-square, does it change the timing of insertion, you think, in High NA? Yeah, so I tried to explain that also in my presentation. The transition, you saw, complex is the whole transition in DRAM. I think our DRAM customer most probably in the course of the next seven, eight years have to make two major transitions, which that's a lot. The transition will not be a cliff. That's the first thing to say. There most probably be an attempt to try to push the existing node as far as you can. Now, when we look at 6F-square versus 4F-square, if I oversimplify a bit, the cost of using EUV on either way, the difference between 4F-square and 6F-square is such that we don't see the transition having a major impact on us. That's a bit the way we look at it in our model because it's not a big change. So there we see a very, I don't know, it is no way a cliff transition. It's a discussion you will have for many, many years to come. I think it will happen. So I think the whole industry will happen. But this doesn't change fundamentally, basically, the need for lithography. All right, maybe one from the online. A few here that are competitive based. Maybe this one to Marco. On the Holistic Lithography, you had e-beam in there. And e-beam, obviously, there's other competitors out there at e-beam. What is it that how does that competitive landscape? How do you describe it in a way where ASML has some advantage over being there versus, say, XYZ competitor? That's a good question. I think if we look to the inspection side, and especially to multibeam, of course, we have been working together with our customers on the existing applications of voltage contrast. So that learnings that we had on the application, we took along in, of course, into basically introduction of multibeam. So that's basically where we, based on the application and working with customers, we could extend on that. And of course, we need to get the technology to be ready and to work for HVM. If you then look at the metrology side of e-beam, I think there, what I showed also in some of the trends, if we really want to characterize edge placement errors, we really need to have massive metrology. And that's out there where our e-beam metrology actually is beneficial because we have a very large field of view. That means with very simple single acquisitions, we get a lot of data. And that's actually we showed also in some of the work we showed with customers; we get basically a lot of data at a very low time, giving us the accurate edge placement maps that we n eed. Very good. And maybe, Herman, this is also a competition question while we're on the topic. We know Canon and Nikon have been in the space for a while, but we also hear about Chinese competitors. Any comments on the competitive dynamic, whether it be inside or outside of China with respect to competitors? Well, one way, of course, as somebody's playing catch-up with you, is to make sure you're staying, that you keep on moving yourself. And I think that's a very important element. And I try to show that also in my presentation by keeping working on the cost, the cost per exposure, the cost of ownership for our customers. This is the way for us to stay competitive. And particularly in some areas, of course, also while going ahead and while applying innovation, you need to learn, right? And in order to need to learn, you need to work with your customers. So for any new entrants in that market, right, it's going to be very important to learn. And we are in a very good position there. We have a huge installed base. So we are actually also using our service people, our application support to work with our customers, actually learn about what our future needs are and innovate based on that. So I think that combination puts us in a quite unique position competitively. Very good. Roger, there's one here on share buyback. With the current stock price, are we looking to do anything accelerating the share buyback? Oh, I feel like a broken record on this one. So the way we do share buybacks is we execute them when there is excess cash, right? And I think the excess cash, I think that goes back to the question that we had earlier on. So we do not opportunistically buy back. We buy back once there is excess cash. I mean, that's our model. And that's what we suggest to continue to do. Okay. We have maybe time for one last question up here. Tammy Qiu from Berenberg. Thank you for squeezing me in. So the first one I have is about the 200K w afers per month below 7 nm capacity addition every single year. Is that mainly relating to end market demand such as AI, or that also includes a big chunk of this geopolitical related regional expansion as well? And how comfortable you are that every year we'll add 200K below 7 nm, please? So just to clarify, the 200K is, I assume you refer to the advanced logic capacity, which was shown there on the slide. And yes, that's purely driven by end markets. The 5%-8% is strategic considerations on top of the end market driven wafer demand. Sorry, just a follow-up. So that 200K is driven by AI and smartphone, etc., for every single year. Do you believe that the visibility is good enough to confirm that that 200K will be built and consumed every single year all the way through 2030? So to be precise, I think it's 240, just to ensure I think I'm getting my numbers right. And yes, it is driven by the end markets, which typically drive advanced logic, are indeed servers, smartphones, and PCs. But as you have seen in the end market view, it's clearly servers where bulk of the growth is coming from. And then, of course, that translates into a significant component of the growth in advanced logic wafers. It is 200 based on the redefinition. Yes. Yeah, based on the redefinition, it is 200. But it's the same question we just had. And we saw it happen. We said we take a not too bullish stance on AI, as we just explained. We heard from the room some people said should it not be bigger. Also, I would say this is what we model on an average basis. Of course, there can be swings per year, obviously, right? So that should also be taken into consideration because at the end of the day, what we give you is a 2030 view, right? We're not giving you a view for every single year. I think that's important to recognize as well. Okay, amazing. And lastly, High NA EUV, so you mentioned that the customer has been commenting that the progress is better than they thought. So are we going to see potentially some upside to the insertion layer you are estimating today if the tool is going better than expected? And worst case scenario, if it's not going as per historically hoped in the next few years, are we going to see lower level High NA being compensated by a higher number Low NA tool, or are we just going to see a potential delay of High NA adoption? Well, I think the answer, the second part is if you don't High NA, you will need to use Low NA. and instead of one mask, you will need two or three masks. So High NA number will always translate into Low NA number. Now, on the upside, I think, of course, there is an upside because customers are just starting to expose wafer today. I think what Peter was explaining, I always say we were talking about the backlog before we had on High NA, which is quite significant. All those orders were placed by our customer without even having one data at hand. They started to get data since June. They have been extremely eager to generate data as quickly as possible so that they finalize a bit their own High NA. they decide also to, for the foundry customer, bring this opportunity to their customer, right? They get their process design kit also to their customer. That creates by itself more opportunity, right? I will say if customers continue like High NA, if they continue to believe, as we do, that there is a benefit in terms of cost, in terms of yield, in terms of lead time to use it, I think they will use it more. We are just at the beginning of this phase where, I think Peter said it very well in his presentation, data starts to speak. Everything we have showed until now was just based on what I call the top-down models, which still makes sense. But now I think the data are starting to change the dynamic. And that's a very important for High NA for sure. All right. I need to now formally close the event. Thank you all for your questions. And I'd like to also say that for any of you on the webcast, if you're unable to get your questions answered, please reach out to your investor relations team. For all you here in the audience, obviously, we'll have opportunities as we go out for drinks and dinner here a little later. Now, with that, I'd like to formally close the program. And on behalf of ASML, I'd like to say thank you all for joining us today.