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INVESTOR DAY PRESENTATION June 12, 2025
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Safe Harbor Statement June 12, 2025 2 This presentation contains statements about management's future expectations, plans and prospects of our business that constitute forward-looking statements, which are found in various places throughout the presentation, including, but not limited to, statements relating to expectations of orders, net sales, product shipments, expenses, timing of purchases of assembly equipment by customers, gross margins, operating results and capital expenditures. The use of words such as “anticipate”, “estimate”, “expect”, “can”, “intend”, “believes”, “may”, “plan”, “predict”, “project”, “forecast”, “will”, “would”, and similar expressions are intended to identify forward-looking statements, although not all forward-looking statements contain these identifying words. The financial guidance set forth under the heading “Outlook” contains such forward-looking statements. While these forward-looking statements represent our judgments and expectations concerning the development of our business, a number of risks, uncertainties and other important factors could cause actual developments and results to differ materially from those contained in forward-looking statements, including any inability to maintain continued demand for our products; failure of anticipated orders to materialize or postponement or cancellation of orders, generally without charges; the volatility in the demand for semiconductors and our products and services; the extent and duration of the COVID-19 and other global pandemics and the associated adverse impacts on the global economy, financial markets, global supply chains and our operations as well as those of our customers and suppliers; failure to develop new and enhanced products and introduce them at competitive price levels; failure to adequately decrease costs and expenses as revenues decline; loss of significant customers, including through industry consolidation or the emergence of industry alliances; lengthening of the sales cycle; acts of terrorism and violence; disruption or failure of our information technology systems; consolidation activity and industry alliances in the semiconductor industry that may result in further increased customer concentration, inability to forecast demand and inventory levels for our products; the integrity of product pricing and protection of our intellectual property in foreign jurisdictions; risks, such as changes in trade regulations, conflict minerals regulations, currency fluctuations, political instability and war, associated with substantial foreign customers, suppliers and foreign manufacturing operations, particularly to the extent occurring in the Asia Pacific region where we have a substantial portion of our production facilities; potential instability in foreign capital markets; the risk of failure to successfully manage our diverse operations; any inability to attract and retain skilled personnel, including as a result of restrictions on immigration, travel or the availability of visas for skilled technology workers. In addition, the United States and other countries have recently levied tariffs and taxes on certain goods and could significantly increase or impose new tariffs on a broad array of goods. They have imposed, and may continue to impose, new trade restrictions and export regulations. Increased or new tariffs and additional taxes, including any retaliatory measures, trade restrictions and export regulations, could negatively impact end-user demand and customer investment in semiconductor equipment, increase Besi’s supply chain complexity and manufacturing costs, decrease margins, reduce the competitiveness of our products or restrict our ability to sell products, provide services or purchase necessary equipment and supplies. Any or all of the foregoing factor could have a material and adverse effect on our business, results of operations or financial condition. In addition, investors should consider those additional risk factors set forth in Besi's annual report for the year ended December 31, 2024 and other key factors that could adversely affect our businesses and financial performance contained in our filings and reports, including our statutory consolidated statements. We expressly disclaim any obligation to update or alter our forward-looking statements whether as a result of new information, future events or otherwise.
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Agenda June 12, 2025 3 I. Strategic Overview Richard Blickman 13.00 – 13.20 II. Market Trends Chris Scanlan 13.20 – 13.50 III. Wafer Level Assembly Peter Wiedner 13.50 – 14.15 Break 14.15 – 14.30 IV. Mainstream Die Attach Christoph Scheiring 14.30 – 14.45 V. Strategic Plan Update Richard Blickman 14.45 – 15.00 VI. Q&A Besi Team 15.00
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June 12, 2025 4 I. STRATEGIC OVERVIEW Richard Blickman CEO
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June 12, 2025 5 • Generative AI accelerating. Large capex budgets maintained by hyperscalers • New use cases emerging from cloud to edge computing • Accelerated advanced packaging innovation expected in 2026-2030 across logic, memory, consumer & I/O • Advanced packaging one of key differentiators to realize AI promise including energy efficient performance in data centers and new consumer edge AI devices AI Expansion Drives Continued Advanced Packaging Adoption • Promise of AI requires new 2.5D/3D assembly solutions to further Moore’s Law • Leading logic players in early commercial production of 3D hybrid bonded devices for data center CPUs and GPUs • New photonics use cases emerging utilizing co-packaged optics (CPO) with hybrid bonding • ASIC usage of hybrid bonding anticipated next year • HBM4/5 requires most advanced processes including hybrid bonding and TCB Next • Next generation CoWoS-L/R structures evaluating TCB Next, next gen Flip Chip and MMA solutions Assembly at Major Growth Inflection Point Besi’s Opportunity
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Many New Advanced Packaging Fabs Planned June 12, 2025 6 Source: TechInsights, Besi May 2025 Packaging Fab Project Initiated Cost ($B) Status Packaging Fab Project Initiated Cost ($B) Status TSMC AP7 CoWoS & SoIC - Chiayi, Taiwan 2024 15,0 In Progress SPIL – Changhua & Yunlin, Taiwan 2025 3,3 In Progress TSMC AP – Arizona, USA 2025 ~10,0 Planned SPIL P1 - Pulau Pinang, Malaysia 2024 1,3 In Progress TSMC AP8 CoWoS – Tainan, Taiwan 2024 7,7 In Progress SPIL – Houli Plant, Douliu Plant Taiwan 2024 0,1 In Progress Intel - Penang, Malaysia 2022 7,1 On Hold Silicon Box - Italy 2024 3,6 Planned Intel - Wrocław West, Poland 2023 4,6 On Hold Tata TSAT - Assam, India 2024 3,2 Planned Intel Fab 11x - New Mexico, USA 2021 4,0 Ramping Amkor Technology – Arizona, USA 2024 2,0 Planned Intel – Chengdu, China 2025 0,3 Planned SJ Semi AP – Jiangyin, China 2023 1,4 In Progress SK Hynix HBM - Indiana, USA 2024 3,9 Planned JCET WLP – Jiangsu, China 2024 1,4 In Progress SK Hynix M15 Expansion - South Korea 2024 1,0 In Progress HT Tech AP – Nanjing, China 2024 1,4 In Progress Samsung - Cheonan, South Korea 2024 8,1 Planned TFME AP – Tongda, China 2024 1,0 In Progress Samsung - Texas, USA 2024 4,0 Planned Hana Micron – Vietnam 2025 1,0 Planned Micron - Singapore 2025 7,0 Planned Global Foundries AP – New York, USA 2025 0,6 Planned Micron - Gujarat, India 2023 2,8 In Progress Amkor + AICEP – Portugal 2024 0,4 In Progress Micron - Xi’an, China 2023 0,6 In Progress Foxconn EU 2025 0,3 Planning STMicro – Catania, Italy 2024 5,0 Planned JCET (automotive) - Shanghai, China 2023 0,2 In Progress Approximately $100B investment in progress or planned
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51.9 56.9 64.4 72.9 78.6 - 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 2024E 2025E 2026E 2027E 2028E $ billions Other 2.5D/3D Total Source: Yole, December 2024 Market Revenue CAGR 2.5D/3D 18.9% Other Advanced Packaging 7.8% Besi Portfolio Well Positioned by Node Size and Accuracy • ~70% of Besi equipment revenue from advanced packaging • ~50% equipment revenue from advanced die placement (< 7 micron accuracy) • ~50% of revenue AI-related • Entering Fluxless TCB market Advanced Packaging Revenue Forecast to Grow Rapidly 2.5D/3D Fastest Growing Segment 7June 12, 2025
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Besi Focuses on Highest Growth Segments of Advanced Packaging 8 TCB Fluxless 450 HB 1,200 €1,650 MM Hybrid bonding estimated to be largest assembly segment by 2030 • Assumes transition from TCB to hybrid bonding as from HBM5 • Estimated market size in 2030 =~350 units (mid case) Besi entering Fluxless TCB market • Emerging market with significant growth potential • Focused on highest value added advanced chiplet and memory applications • Estimated market size in 2030=~100 units (mid case) Source: Besi estimates. Mid case scenario hybrid bonding Estimated 2030 Hybrid Bonding & TCB Fluxless Market Size (€ MMs) June 12, 2025
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81% 79% 78% 81% 82% 2020 2021 2022 2023 2024 37% 40% 40% 46% 50% 2020 2021 2022 2023 2024 Besi’s Die Attach Market Share Trends Source: TechInsights, June 2025 1) Excludes TCB, wire bonding, dicing, and other 2) Advanced die placement defined as < 7 micron accuracy per TechInsights Die Attach1 Advanced Die Placement1,2 9June 12, 2025
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Strategic Objectives Maintain best in class technology leadership Expand presence in wafer level assembly Increase market presence in addressable markets Enhance scalability and reduce structural costs Exceed challenging sustainability metrics for 2026 and 2030 Acquire companies with complementary technologies and products Reward shareholders via capital allocation policy Summary Strategy 10 Strategic focus/discipline has been a winning formula: • Maintain position as R&D leader • Focus on advanced packaging • Win with the winners • Seek profit over market share • Provide leading-edge systems at mainstream cost structure and lead times • Keep highly flexible and scalable production model • Grow in sustainable manner June 12, 2025
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Expansion of R&D Spending in Support of New Product Introductions 38.4 78.7 10.8% 13.0% 0% 5% 10% 15% 20% 0 10 20 30 40 50 60 70 80 90 2019 2024 € millions Gross R&D* % of Revenue * Gross R&D spending excludes impact from capitalization/amortization of R&D costs 11 Innovation is a key driver of our business: • New opportunities for each next-generation advanced packaging system Significant R&D investment in advanced packaging over past 5 years to support: • New 2.5D/3D IC assembly structures for AI • Portfolio enhancements for next market upcycle Key areas of current focus: • 50 nm accuracy hybrid bonder • TCB Next for memory and logic applications • Advanced CoWoS: • 1 micron accuracy Evo • Next gen flip chip June 12, 2025
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Higher Through Cycle Revenue and Gross Margins 12 191 351 379 593 749 605 164 302 516 424 64.3% 34.1% 39.5% 58.0% 51.1% 0% 10% 20% 30% 40% 50% 60% 70% 0 100 200 300 400 500 600 700 800 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 LTM* Revenue Gross Margin€ millions 4 year averages Gross Margin * LTM per Q1-25 June 12, 2025
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13 II. MARKET TRENDS Chris Scanlan Senior VP Technology June 12, 2025
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AI is Driving Long-Term Semiconductor Revenue Growth 14 Data Center AI Infrastructure AI Personal Computers AI Smartphones AI Wearables (AR/VR) Autonomous Taxis Humanoid Robotics $- $0.2 $0.4 $0.6 $0.8 $1.0 $1.2 $1.4 2000 2005 2010 2015 2020 2025 2030 2035 Semiconductor Revenue ($T) CAGR 2024 - 2033 Total Semiconductor Market 6.8% AI-Related Semiconductors 28.9% Non-AI AI Sources: TechInsights 2025, Precedence Research Nov 2024 June 12, 2025
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And Growth in Besi’s Principal End-User Markets 15 Mobile Internet (20%)Computing (43%) Industrial/Other (9%) Lidar Automotive (12%) Percentages based on 2024 estimated revenue per end market application. Spares/service revenue was ~16% of 2024 revenue AI Smartphone AR/VR Headsets Camera Technology 5G Advanced → 6G Agentic AI Training and Inference AI Enabled PC Si Photonics Autonomous Driving Vehicle Electrification Connectivity Infotainment Robotics Smart Grid Industrial IoT Clean Energy June 12, 2025
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0 500 1000 1500 2000 2500 3000 3500 4000 2005 2010 2015 2020 2025 2030 Die Area (mm2) Die Sizes Exceeding Reticle Limits Reticle Size Limit NVIDIA Rubin Ultra (E) NVIDIA Blackwell H100 • Moore’s Law slowing as data volumes grow exponentially and commercial applications expand • Customers adopting chiplets, connected via hybrid bonding and TCB, to optimize device function per node and reduce cost Slowing of Moore’s Law Accelerates Adoption of Chiplets & 3DIC 16 0.01 0.1 1 10 100 1000 2000 2010 2020 2030 Transistor Density (MTr/mm2) Transistor Density Slowing Source: IRDS 2023 Edition Source: Tom’s Hardware, IEDM 2023 - Google 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2005 2010 2015 2020 2025 2030 Cost per Transistor per 100M Gates (rel. cost) Cost per Transistor Increasing 0 50 100 150 200 250 300 350 400Chiplet Revenue ($ Billion) Chiplet Usage Expected to Grow Rapidly Chiplet CAGR 48.1% (2024 – 2033) Source: Dimension Market Research January 2025 June 12, 2025 Source: Besi
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Latest Advanced Data Center Chips Adopting Chiplet Architectures 17 AMD NVIDIA Intel B100 (Blackwell) GPU CoWoS-L package Gaudi 3 AI Accelerator CoWoS-S package Clearwater Forest CPU Foveros Direct (Hybrid Bonding) Spectrum X Network Switch CoWoS-S with CPO (Hybrid Bonding) MI325 GPU CoWoS-S (Hybrid Bonding) Zen 5 EPYC CPU SoIC (Hybrid Bonding) June 12, 2025
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• Escalating cost with each new advanced node • Chiplet benefits: • Improved yield and cost efficiency • Increased energy efficient performance • Increased design flexibility • Faster time to market • Scalability AMD Demonstrating Value of Chiplets Across CPU Roadmap 18 AI Data Center EPYC 9004 Series Gaming PC Ryzen 9 9900X3D AMD Zen5 3D CCD Chiplet using Hybrid Bonding SRAM chiplet on bottom Compute chiplet on top General Purpose Server EPYC 4585PX 0 5000 10000 15000 20000 25000 30000 90nm 65nm 40nm 28nm 20nm 12nm 10nm 7nm 5nm 3nm 2nm Price ($) Est. Wafer Cost per Node Source: anysilicon.com 5nm? 7nm? Source: AMD 4nm 6nm June 12, 2025
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Chiplet Usage Also Drives Demand for Advanced Die Attach Equipment Source: Intel DozensDie attach steps1 100nmAccuracy10µm Monolithic: Integrated SoC Multiple Dies: node optimized Individual IPs: node optimized Single Chip Design Multi Chip Module 3D Multi Chiplet System 19 June 12, 2025
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AI Chiplet Packages Require a Variety of Advanced Packaging Solutions 20 Thermo-compression Bonding CoW Flip-chip and Fan-outHybrid Bonding Flip-chip CoS Advanced mass reflow flip- chip attach > 40 um pitch Photonics High precision optical component placement Interposer Attach oS bonding of large interposers up to 110 mm Chiplet Molding CoW encapsulation CoWoS molded underfill 3DIC stacking < 9μm pitch HBM stacking ≥ 16 High Photonics C2W chiplet stacking HBM stacking ≤ 16 High 3D bridge attach CoW flip-chip of logic & memory High-density fan-out Embedded bridge die attach June 12, 2025
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Besi Developing Complete Portfolio for Complex AI Chiplet Packages 21 Thermo-compression Bonding 9800 TC Next CoW Flip-chip and Fan-out 8800 CHAMEO fleX Flip-chip CoS 8800 Quantum AdvX Photonics 2200 evo 1μm Interposer Attach 2200 evo Advanced Chiplet Molding xMS-NXT 8800 CHAMEO UltraPlus AC New Q1-26 New Q1-26 R&D Hybrid Bonding June 12, 2025
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TCB Micro-bump C2W TCB C2W used for lower density, less performance critical applications, such as CoW interposer assembly Hybrid Bonding is Technology of Choice for High Performance Logic Chiplet Stacking 22 Micro-bump C2W TCB Performance Factor* Hybrid Bonding 1X Interconnect Density 15X 1X Speed 11.9X 1X Bandwidth Density 191X 1X Energy Efficient Performance, EEP** >100X 10X Cost per Interconnect*** 1X Data source: * TSMC 2023, ** TSMC 2025, ***Besi estimate based on max interconnect density Hybrid Bonding Highest performance interconnect to create 3D ICs in front-end wafer fabrication process Source: INTEL Source: INTEL June 12, 2025
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Intel using hybrid bonding to stack CPU core chiplets atop base tiles with SRAM and I/O functions 3D stacking “improves the latency between compute and memory by shortening the hops, while at the same time enabling a larger cache” - Pushkar Ranade, Intel Intel Introducing New Products Using Hybrid Bonding 23 12 CPU chiplets on Intel 18A node 3D stacking of CPU chiplets to base die using hybrid bonding Total 300 billion transistors Source: Intel Clearwater Forest Data Center CPU (2025) June 12, 2025
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• Broadcom co-develops AI chips for customers such as Google, Fujitsu, Apple and Open AI • Announced use of hybrid bonding for custom AI ASICs • Using TSMC’s SoIC process with face-to-face hybrid bonding • Initially at 6 micron bond pad pitch • Production estimated to begin in 2026 New Hybrid Bonding Applications Expected to Ramp in Near Term 24 Source: Broadcom Source: https://9to5mac.com/2024/12/23/m5-pro-chip-could-separate-cpu-and-gpu-in-server- grade-chips/ June 12, 2025
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NVIDIA using hybrid bonding in new network switch products using co- packaged optics (CPO) CPO Use Cases Emerging in New Product Announcements 25 Spectrum-X Ethernet switch with 36 CPO chiplets Quantum-X800 InfiniBand switch with 18 OE chiplets Source: Broadcom Broadcom’s CPO network switches utilize multiple advanced flip-chip bonding processes Hybrid Bonding Source: TSMC, ECTC 2025 • Based on TSMC’s COUPE technology that uses hybrid bonding • Up to 36 hybrid bonded chiplets per switch device • Should help drive significant hybrid bonding capacity expansion through 2030 - 10 20 30 40 50 60 70 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 Number of Units (MM) CPO Optical Engine Shipments Source: Yole CPO 2025 CAGR 2024 – 2035 100% June 12, 2025
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Leading integrated hybrid bonding system for HBM stacking Orders from 2 major memory customers Well positioned to win in TCB with highest accuracy, quality and productivity Orders from 3 major logic and memory customers and IMEC HBM Bonding Technology Roadmap and Besi´s Opportunity HBM3 HBM3e HBM4 HBM4e HBM5 Year of Release 2023 2024 2025 2026 2028 Besi Opportunity C2W TCB Hybrid Bonding # of Dies TCB 8 12 16 16 - Hybrid 16 ≥20 Interconnect Pitch 25µm 22µm 20µm 18µm <15µm Base die technology ≥12nm IDM buffer die ≤ 4nm advanced foundry logic * NCF = non conductive film ** MUF = molded underfill Fluxless TCB-MUF Source: SKHynix TCB-NCF Source: TechInsights Hybrid Bonding Source: Samsung 16 DRAM Dies Base Die Bond Interface June 12, 2025 26
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Use of advanced logic nodes for the HBM base die is planned from HBM4 onwards • Additional compute functionality will be added to the base die, increasing thermal power dissipation requirements • Hybrid bonding necessary to overcome the thermal performance bottleneck to enable higher logic power density Hybrid Bonding Enables Next Generation HBM to Incorporate Higher Performance, Custom Logic Base Die 27 No solution with μBump 1 Source: “Innovative SoIC® Cool-Stacking Technology to Overcome the Thermal Wall of Future High-Performance Compute” TSMC, 2025 ECTCSource: AMD Hybrid bonding with enhanced interface layer reduces thermal resistance by 4x and improves EEP by >100x compared to μbump.1 “Micro-bump is not capable of providing decent design flexibility for any ambitious next-generation HBM.” – TSMC1 June 12, 2025
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0 300 600 900 1200 1500 2024 2025 2026 2027 2028 No. of Smartphones (MMu) Est. GenAI Smartphones Traditional Smartphones Future Chiplet APU Devices with Wafer Level Assembly (2027-28E) GenAI enabled smartphone market expected to grow at 41.4% CAGR 2024-2028 • Will require processors with more NPU power and more memory with higher bandwidth connection to the APU • Adoption of chiplet architectures for the APU and new memory packaging to fit more chips in the same vertical space AI enabled phones will require 2.5D and 3D chiplets assembled on wafer level using flip-chip, TCB and hybrid bonding • Should drive major upgrade cycle for APU packaging with opportunities for Besi’s CHAMEO fleX, TC Next and hybrid bonding AI Enabled Smartphones Also Expected to Adopt Chiplet Solutions 28 Source: IDC July 2024, TSMC CAGR 2024 – 2028E Gen AI Smartphone 41.4% Total Smartphone 2.2% Current Mobile APU with Single SoC InFO PoP (Apple A18) MCeP (Qualcomm, Mediatek, HiSilicon) Source: Techsearch CoW-R SoIC X/P Wafer level RDL Chiplet 1 Chiplet 2 8800 CHAMEO fleX CoW SoIC Chiplet 1 Chiplet 2 Chiplet 3 Wafer level RDL Hybrid Bonding, TC Next 0M 100M 200M 300M 2024 2028 2030 No. of Units Significant Growth in 3D SoIC Mobile & Consumer Source: Yole May 2025 June 12, 2025
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Summary 29 Rapid advancements in AI technology and applications driving growth in all Besi end- user markets Besi’s R&D focused on providing 2.5D and 3D interconnect solutions for high performance AI enabled devices Accelerating adoption of chiplet architectures as Moore’s Law slows Hybrid bonding is highest-performance, most energy-efficient interconnect technology with lowest cost-per-interconnect TCB C2W is an emerging process technology with significant market potential Besi is well positioned to win market share as the high-end assembly market evolves June 12, 2025
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III. WAFER LEVEL ASSEMBLY Peter Wiedner Senior VP Sub-Micron Die Attach 30 June 12, 2025
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Sub-Micron Die Attach Product Portfolio 31 Hybrid Lid AttachThermocompression 8800 CHAMEO ultra plus AC 8800 HYBRID G22026 9800 TC NEXT DLA Line TGB hpNew New June 12, 2025
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Advanced Logic Driving New Fine Pitch Interconnect Technologies June 12, 2025 32 TC fluxless HybridCompute Power migration path Interconnect for computing and HBM • High end semiconductor design following path to tightest interconnect pitch • Hybrid bonding enables bump pitches <10µm • Hybrid bonding facilitates 3D chip designs to extend Moore’s law • TCB fluxless bridges gap between existing flux-based TCB and hybrid bonding interconnect • Besi strategic focus on leading edge hybrid bonding and TC Next
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TC next – Leading TC Bonder for Next Generation Heterogeneous Integration – Designed for Bump Pitches below 10µm 33 Best in Class Performance and CoO4 UPH up to 2,000 Highest Accuracy in Market 1 Accuracy: 0.7µm Bump Pitch: 7-20 µm Best in Class Fluxless Capabilities2 Micro inert chamber and plasma oxide reduction June 12, 2025 Defense: Realtime Process Control for Each Individual Bond3 0 1 2 3 4 application of joint stress solder joint quality with reduction Note: Model & measurement data based adjustment of BLT / bump shape
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Besi Hybrid Bonder – Highest Accuracy and Lowest CoO 34 8800 CHAMEO ultra plus AC Today’s Industry Standard 1 Alignment Accuracy: 100nm Bump Pitch: 6µm June 12, 2025 Logic roadmap – driven by accuracy Memory roadmap – driven by throughput Improving HBM CoO4 • Increasing UPH further to enable cost effective stacking ≥16 high Die stacking UPH: >5,000 8800 HYBRID G2 Launch in 20262 50nm accuracy enables even smaller pad pitches Bump Pitch: 3µm Significantly higher UPH decreases CoO for HBM Die stacking UPH: 3,000 Accuracy 50nm Roadmap to 25nm and beyond3 • Development for 25nm and beyond ongoing Bump Pitch: 1µm • Enabling transistor to transistor interconnect at 1µm pad pitch by 2030
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Hybrid Bonding Will Become Mainstream Advanced Packaging Solution June 12, 2025 35 Reality: HB provides superior cost: • Requires higher infrastructure cost but delivers 10x lower cost per interconnect • Increases energy-efficient device performance by >100x, lowering data center operating cost • Reduces HBM stack temperature by 20%, lowering system cooling cost • Provides flexibility to combine most cost-efficient silicon nodes • First commercial product with hybrid interconnect was a consumer-oriented gaming CPU (AMD Ryzen) In addition: HB essential to semiconductor and system design progress: • Enables more energy-efficient performance and the extension of Moore’s law • Enables HBM roadmap and tighter integration of optical and mixed signals Perception: Hybrid bonding is too expensive for widespread adoption
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Hybrid Interconnect AI Use Cases are Solidifying • Accelerated AI usage. Increased focus on energy efficient AI chips • Hyperscalers like Meta and Google designing proprietary AI XPUs • TSMC opening a new packaging factory for SOIC in 2026 0 100 200 300 400 500 600 CMD 2024 CMD 2025 Hybrid Unit Forecast: AI Logic (Cumulative 2025-2030) Application Drivers: AI Logic 36 Source: Besi estimates, June 2025 June 12, 2025
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0 100 200 300 400 500 600 CMD 2024 CMD 2025 Hybrid Unit Forecast: HBM (Cumulative 2025-2030) Application Drivers: High Bandwidth Memory 37 • Overall HBM demand is forecast to increase 4x 2025 - 2030 • TC and TC-fluxless will be primary technologies used through HBM4 • Hybrid bonding investments will start in 2026 accelerating in 2027/2028 • By 2030, majority of capex will be focused on hybrid stacking for 16+ high memory stacks • TC NEXT investments in 2030 will be focused on replacing older TC technologies for medium-sized memory stacks 0 50 100 150 200 250 300 350 CMD 2025 TC-Fluxless Unit Forecast: HBM (Cumulative 2025-2030) NEW Source: Besi estimates, June 2025 June 12, 2025
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Optical links now used to replace copper for short distance data transfer to connect individual boards within datacenters • Can achieve higher bandwidth at lower energy consumption (up to 80% savings) • Hybrid technology being used in CPO to connect the photonic IC with the electrical IC @ high speed 0 10 20 30 40 50 60 CMD 2024 CMD 2025 CPO Hybrid Unit Forecast: CPO (Cumulative 2025-2030) Application Drivers: Co-Packaged Optics 38 • At GTC 2025, NVIDIA revealed use of CPO in their photonics network switches “Spectrum-X” and “Quantum-X” • Broadcom announced its new Tomahawk 6 switch • “For systems requiring optical connectivity, Tomahawk 6 will also be available with co-packaged optics, providing the lowest power and latency” • TSMC launched a CPO package called COUPE. Available for all photonics customers Source: Besi estimates, June 2025 NEW June 12, 2025
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0 100 200 300 400 CMD 2024 CMD 2025 Hybrid Unit Forecast: Consumer Logic (Cumulative 2025-2030) Application Drivers: Consumer: PCs - Tablets – Smartphones 39 • Adoption of edge AI driving need for energy-efficient performance beyond datacenters to also include consumer devices • This will drive growth in both hybrid bonding and TC-fluxless • Hybrid chiplet interconnect will be used for the most advanced edge-AI applications • TC NEXT will cover the mid-range of application processors 0 50 100 150 200 CMD 2025 TC-fluxless Unit Forecast: Consumer Logic (Cumulative 2025-2030) Source: Besi estimates, June 2025 NEW June 12, 2025
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New application fields emerging: • Advanced micro displays for smart glasses are using hybrid and fusion bonding technologies • Enables smart glasses comparable in size to conventional glasses 0 5 10 15 20 25 30 CMD 2024 CMD 2025 Hybrid Unit Forecast: AR Glasses (Cumulative 2025-2030) Smart glasses prototype Application Drivers: Consumer: AR Glasses – Optical Applications 40 Source: Besi estimates, June 2025 NEW June 12, 2025
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Applied Materials & Besi Collaboration Helps Accelerate Hybrid Bonding Adoption and Growth, 2 to 4 generations ahead 41 • Front & Back End Process & Equipment Expertise • Market Leader in Advanced Wafer Level Packaging • Dedicated Packaging Development Center in Singapore • Collaboration Extended Another 5 years ▪ Back End Assembly Equipment & Process Expertise ▪ Market Leader in Hybrid Bonding Systems Collaborative Accelerated Innovation June 12, 2025
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0 100 200 300 400 500 600 700 2024 2025 2026 2027 2028 2029 2030 Total # of installed TC fluxless C2W machines Fluxless TCB C2W Market Potential 42 Fluxless TCB applications bridge gap between conventional TCB and hybrid bonding Memory: • Next generation AI devices driving strong HBM demand in near term • Increased HBM stacking requirements driving TC technology towards fluxless Logic: • Requirements for increased accuracy and chiplet architectures driving conversion of mid-end logic applications from mass reflow flip-chip to TC fluxless Low case Mid case Estimated 350 – 600 systems cumulatively by 2030 Source: Besi estimates, June 2025 Development Logic Memory High case Volume Production June 12, 2025 Development Volume Production
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0 200 400 600 800 1000 1200 1400 1600 1800 2000 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 Installed Base Hybrid Bonding Systems (#Units) Hybrid Bonding Market Potential – Logic and Memory Cases Confirmed 43 Low case (logic): • Logic adoption confirmed • AMD and Intel progressing as expected • Broadcom adopting SoIC for custom AI ASICs • High-end PC/laptop CPUs expected to adopt SoIC by end of 2025 • Many AI device players in development Mid case (Memory & CPO): • Memory adoption confirmed • All leading players evaluating both HB and TCB for HBM4 • First hybrid bonded HBM4e 16 high stacks in 2026 • HBM 5: Hybrid bonding only • Co-packed optics moves from upside potential to reality High case: • Emerging applications becoming more tangible • Smart glasses adopting D2W fusion bonding • Micro displays • Sensors • Smartphones Low case Mid case Estimated 960 – 2,000 systems cumulatively by 2030 Up ~7% for low and mid cases vs. 2024 CMD Source: Besi estimates, June 2025 Development Logic Volume ProductionDevelopment Memory High case Volume ProductionDevelopment Volume Production Mobile Consumer June 12, 2025
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IV. MAINSTREAM DIE ATTACH Christoph Scheiring Senior VP Die Attach 44 June 12, 2025
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Besi’s Mainstream DA Addressable Market* Expected to More Than Double by 2030. Growth Anticipated Across All Product Lines June 12, 2025 45 Key Market Trends • Exponential growth in AI training workloads drives data center expansion and demand for HPC and Photonics • Move to Inferencing expected to drive next wave of equipment demand as applications deployed at scale • Increasing inference requirements will drive upside for mainstream CPUs and ASICs • Gen AI applications and edge AI demand expected to drive mainstream consumer and industrial market • PC, Mobile, IoT Sensors, Automotive • Push for performance, efficient power and miniaturization favors Besi’s core advanced packaging solutions such as flip chip Growth accelerating across all end user markets Source: Allianz Research, 2025 Source: Besi / Techinsights June 2025 * Excluding TCB, Hybrid, Die Sorting, LED 660 1’480
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Industry Leading Mainstream Die Attach Equipment Portfolio with Significant Competitive Advantage Flip Chip EpoxySoft Solder Multi- module 46 ▪ Highest accuracy for photonics and CPO ▪ Leading process capabilities for large die AI interposer attach and advanced camera modules ▪ Industry leading accuracy and speed in epoxy die attach ▪ Stringent epoxy control for mobile and automotive power and sensor applications ▪ Leading soft solder process (oxygen level, gas consumption) for automotive power applications ▪ Unique diffusion solder process offering ▪ Highest accuracy C2W (2.5D CoWoS) assembly ▪ Highly productive tool of reference in BGA & CSP & LF flip chip attach ▪ New tailored high speed solution for camera modules June 12, 2025
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CAGR 2024 – 2030E 17.0% Portfolio Well Positioned in High Growth 2.5D Advanced Packaging 2.5D package architectures require new flip-chip capabilities to support multiple chiplets including higher accuracy, higher productivity and greater flexibility 47 High Speed CoW (Logic & HBM) 2200 Evo advanced Large Die Interposer Attach • Large die flip chip • 110mm x 110mm • OHT integration • Placement accuracy 3um • High speed flip chip attach • Inline wafer and tape and reel configuration NEW 8800 Chameo Flex (2026) • Highest productivity/integrated CoW solution • Placement accuracy 1um • Full front-end automation 0 2 4 6 8 10 12 2024 2030 Revenue ($B) 2.5D Logic Packaging Revenue Growth Source: Yole, High End Performance Packaging 2025 8800 Chameo advanced / TnR June 12, 2025
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Transceivers* 628 Transceivers 564 Memory 384 Compute 360 #DA Steps per Tray NVIDIA NVL72 Besi’s Multi Module Attach System: Leading Photonics Platform in Rapidly Growing Market • Best combination of placement accuracy and productivity • Versatility in complex system assembly • Ultimate process control • Significant installed base with industry leaders NEW Evo 1um (2026) Introducing new 1um accuracy system (replacing active alignment) to increase optical transceiver market share Typical Optical Transceiver Assembly Computer 48 Optical transceivers in today’s AI servers require a significant number of die attach steps Data center expansion driving demand for optical connections NVIDIA NVL72 Source: Nvidia 2200 Evo advanced Source: BESI Besi # 1 player in optical transceiver assembly working with all key players * Currently not addressed June 12, 2025
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Edge AI Drives Semiconductor Market Recovery and Demand for Besi Mainstream Die Attach Equipment 49 2200 evo 2100 hSi / SSI / FC 8800 FCQ / Chameo / CIS Application Drivers • Processors (Mobile AP, GPU, CPU, ASIC) • DRAM NEW 8800 CIS • Introduction of high- speed platform for advanced camera module assembly Application Drivers • Smartphone camera • Automotive and industrial power modules • AR/VR devices Application Drivers • Mobile RF power amplifiers • Mobile sensors • Power management ICs • AI drives high-end smartphone segment with richer content (AP, memory, camera) • New camera applications in pipeline (mechanical aperture, stacked lens assemblies) Source: Cambridge Mechatronics • AI gaining traction in automotive sector (from driver assisted systems to autonomous vehicles) • Advanced packaging enabled electronic content in cars is increasing 0 200 400 600 800 1000 2024 2028 No. of Units (M) 0 20 40 60 80 2024 2035 No. of Units (M) Self Driving Cars 0 5 10 15 20 25 2024 2028 No. of Units (M) AR/VR Source: IDC July 2024 Source: MarketsandMarkets Dec 2024 Source: IDC Dec 2024 GenAI Smartphones CAGR 2024 – 2028 40.5% CAGR 2024 – 2035 6.8% CAGR 2024 – 2028 31.2% • AI in combination with AR/VR is changing how people interact with the digital world • AR/VR HW requires new forms of miniaturized, energy efficient, high- performance packaging Besi Mainstream die attach solutions are preferred choice for AI driven advanced packaging needs June 12, 2025
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Summary 50 • AI driving customer investments in next generation devices and applications requiring advanced packaging • Besi’s mainstream die bonding addressable market expected to more than double by 2030 • Favorably positioned in highest growth segments of advanced packaging: • CoWoS • Photonics • Mobile • EV/autonomous driving • New product introductions in 2025-2026 expected to accelerate growth and increase market share June 12, 2025
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51 V. STRATEGIC PLAN UPDATE Richard Blickman CEO June 12, 2025
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Strategic Plan Updated to Position Besi for Advanced Packaging Growth 2025-2030 52 Strategic Plan Update 2025 • 16-week process • Senior management, customers and other key stakeholders involved • Revenue and cost reduction goals established • Multiple secular growth drivers identified: • Expanded AI deployment and use cases across principal end user markets • Increased chiplet adoption for heterogeneous integration • Increased HB and TCB Next adoption for <3 nm node sizes • Increased investment in advanced packaging fabs • Capacity, personnel planned to meet growth expectations June 12, 2025
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Long-Term Market Opportunity 53 5.1 5.5 6.3 8.2 2024E 2025E 2026E 2029E Source: TechInsights, June 2025. Assembly equipment revenue excludes service revenue Long-term growth trends intact: • Expansion of AI/use cases • Advanced packaging growth in all end-user markets Significant assembly growth forecast between 2024-2029 • 25% increase anticipated 2024-2026 • AI and cyclical mainstream recovery • 63% increase expected 2024-2029 Besi expects to significantly outperform overall growth rate for assembly equipment market 8.9% 15.0%Growth Rate 30.0% June 12, 2025
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54 Target Model Update Prior Long Term Target € 1 billion +++ 40%+ 62-66% 35-50% Net Zero GHG by 2030 100% from renewable sources Revenue Addressable Market Share Gross Margin Operating Margin Scope 1 & 2 Emissions Global Energy Needs New Long Term Target € 1.5-1.9 billion 40%+ 64-68% 40-55% Net Zero GHG by 2030 100% from renewable sources June 12, 2025
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Key Revenue Growth Drivers 55 1.0+++ Old New Revenue Target € Billions 1.5-1.9 • Expanded logic adoption as new use cases emerge • Heterogeneous chiplet integration, datacenter, Edge AI, CPO • Expanded consumer applications for mobile, PCs, wearables, AR/VR • Memory adoption for HBM 4/5 • Increased market penetration via Applied Materials integrated production lines Hybrid Bonding • Transition from Chip to Substrate to Chip to Wafer at leading edge • Expanded use in HBM 4 and advanced CoWoS applications • Significant upside market share potential TCB Next • Increased penetration of photonics, smart phone, power module and mobile memory markets with next gen multi module and flip chip systems • New mobile innovation: advanced cameras, sensors, AP packaging and phone form factor • Packaging: Chiplet molding and singulation, SiC and GaN power device molding • EV and autonomous driving Advanced 2.5D / Mainstream Spares/Service growth scales with expansion of sub-micron die attach installed base June 12, 2025
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Key Operational Goals 56 Gross Margin • Target € 15-30 million cost reduction • Realize further design efficiencies via common parts/platforms/modules Operating Expenses • Investment in R&D and Service/Support to support sub-micron die attach growth • Limit G&A growth to rate of inflation Operations • Expand presence in SE Asia and India per customer roadmaps • Increase cleanroom capabilities Sustainability • Net zero GhG emissions by 2030 • 100% global energy needs from renewable sources June 12, 2025
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Strong Liquidity Position for Future Growth Attractive Capital Allocation Policy Continues 57 Shareholder friendly capital allocation • € 2.2 billion distributions since 2011* • Equal to ~33% of cumulative revenue • € 22.1 million distributed YTD Q1-25 • € 51.4 million purchased under current € 100 million share repurchase program • Treasury shares equal 2.0% of TSO Attractive funding to help finance growth: • € 197.7 million Convertible Notes • Blended interest rate 1.74% • € 350 million 4.5% Senior Notes due 2031 • € 80 million revolving credit expandable to € 136 million 413.5 672.3 685.7 113.0 143.8 159.4 0 100 200 300 400 500 600 700 800 900 1000 2023 2024* Q1-25 € millions Cash and Deposits Net Cash € 436 million capital allocation € 251 million capital allocation € 22 million capital allocation Q1-25 * Includes dividend paid in May 2025 June 12, 2025
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Summary 58 • AI expansion drives continued advanced packaging adoption • Slowing of Moore’s law accelerating adoption of chiplets and 3D IC Assembly Market at Major Growth Inflection Point • New system introductions planned in 2026 for CoWoS market Besi Developing Complete Portfolio of Complex Chip Packages For World’s Leading Semiconductor Producers • Hybrid bonding and TC Next anticipated to be fastest growing assembly segments over next 5 years • New use cases emerging in logic, CPO, memory and consumer applications • Hybrid bonding market potential increased 7% versus 2024 CMD Hybrid Bonding Technology of Choice for High Performance, Energy Efficient Computing • Long-term revenue, gross margin and operating margins increased reflecting incremental upside potential Strategic Plan Updated to Position Besi for Advanced Packaging Growth 2025-2030 Attractive Capital Allocation Policy Maintained June 12, 2025
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VI. Q&A 59 June 12, 2025
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60 Assembly market ever more critical in semiconductor value chain Disciplined strategic focus has created an industry leader Long term secular trends drive advanced packaging growth Wafer level assembly for AI applications promising new growth opportunity Market presence has grown via key IDMs, supply chains and partners Tech leadership and scalability result in superior financial returns Commitment to sustainable growth and fighting climate change Attractive capital allocation policy Investment Considerations June 12, 2025