Slides
Page 1
eMemoryBriefing.
Page 2
All rights, titles and interests contained in this information, texts, images, figures, tables or other files herein, including, but not limited to, its ownership and the intellectual property rights, are reserved to eMemory Technology Incorporated and PUFsecurity Corporation. This information may contain privileged and confidential information. Any and all information provided herein shall not be disclosed, copied, distributed, reproduced or used in whole or in part without prior written permission of eMemory Technology Incorporated or PUFsecurity Corporation. IPR Notice .
Page 3
. eMemory eMemory: Embedded NVM with Logic Process Part 1. The Core Concept Volatile Memory (e.g., RAM) Non-Volatile Memory (e.g., Flash/Storage) Power Off Data LOST Power Off Data STAYS Part 2. eNVM vs. External Memory External MemoryEmbedded Memory (eNVM) Slower, Higher Power Part 4. Advanced Security Part 2. What eMemory Does One-Time Programmable (OTP): NeoBit (8-inch) NeoFuse (12-inch) Part 3. Key Technology Types Key Uses: • Memory repair for DRAM/SRAM • Image sensor recovery • Analog circuits trimming Integrated eNVM Main Processor SoC Faster, More Efficient, Saves Space Main Processor SoC External Memory Data Logic-Compatible eNVM IP License IPs to Foundries and Chip Designers Key: Enables eNVM in standard logic processes, WITHOUT extra costly steps. (Cost-Effective, Scalable) Key Uses: • Firmware Updates • Data Logging • Flexible Product Configuration Multi-Time Programmable (MTP): NeoFlash NeoMTP NeoEE Embedded ReRAM ASIC Memory Anti-Fuse Technology(OTP) Permanent, difficult-to-tamper connection (better than standard fuse). Highest security. NeoPUF (Physical Unclonable Function) Uses unique microscopic variations to generate keys ON-DEMAND, not stored. Ultimate root of trust. 1
Page 4
. eMemory Revenue Trend (Unit: NT$ in Million) Company Overview 79M+ Spanning 772 production processes from 0.5µm to 2nm, and 5M wafers (8″-equivalent) shipped in 2026 H1. Cumulative Wafers Shipped Best IP Partner with TSMC Founded in 2000 and IPO in 2011. Recognized as TSMC’s Best IP Partner every year since 2010. 16-Year ◼ eMemory leads the global market in Logic NVM and PUF-Based Security IPs. 0 500 1,000 1,500 2,000 2,500 3,000 3,500 4,000 4,500 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 Royalty License/Design Revenue Patents Issued Expanding our IP footprint with 221 pending patents, driven by a 339- member team with 73% R&D focus. 1370+ 2
Page 5
. eMemory T echnology Portfolio ◼ eMemory’s IP portfolio is built on two pillars: OTP as the foundation and MTP for scalable integration. PUFcc NeoBit (OTP) NeoMTP (MTP) NeoEE (MTP) Leading NVM and PUF Technology Innovation Pioneering PUF-Based Security IP Design Embedded ReRAM NeoFlash NeoFuse (OTP) SecureOTP PUFrt 2005 2010 2015 2020 PUFhsm NeoPUF (PUF) 3
Page 6
. eMemory One-Time Programmable (OTP) Memory ◼ eMemory advances silicon security from foundational OTP to next-gen NeoPUF-Based solutions. • NeoBit (8″ Wafer Processes) • NeoFuse (12″ Wafer Processes) OTP From OTP to PUF Crypto - processors Cryptography • NeoPUF • PUFrt • SecureOTP • PUFcc • PUFhsm • RSA • ECC • AES • SHA • PQC • etc. PUF Yield Enhancement • Memory repair for DRAM/SRAM • Image sensor recovery • Analog circuits trimming Fundamental Security • Hardware root-of-trust • Unalterable key storage • Silicon-level identity protection 4
Page 7
. eMemory Evolution from OTP to PUF-HSM ◼ eMemory evolves from OTP technology into integrated PUF-based security subsystem. 5
Page 8
. eMemory Multiple-Time Programmable (MTP) Memory MTP Flash • NeoEE • NeoMTP • NeoFlash • Embedded ReRAM • ASIC Memory Density Variety • Scalable storage configurations • Optimized silicon footprint • Versatile capacity range (Bits to Mb) High Endurance • Optimized write/erase cycles • Enhanced data retention reliability • Extended application operational lifespan Process Integration • Seamless standard logic embedding • Foundry-ready ASIC integration • Zero-mask overhead implementation Logic-compatible MTP 6
Page 9
. eMemory eMemory Enabling AI Memory Systems High Yield, Low Cost High Reliability • PUF-Based Root of Trust: Establishes hardware- anchored trust foundation • Secure Transmission: Protects data integrity across CXL memory pools • Storage Protection: Safeguards AI models within NVMe/SSD controllers • Repair Integration: Ensures HBM stack and DRAM integrity • Data Retention: Guarantees long-term stability via OTP redundancy • Workload Stability: Supports operational uptime under extreme AI tasks • OTP Repair: Enhances SRAM/HBM/DRAM production yield • MTP Configuration: Optimizes updateable DDR5/SOCAMM DIMMs • Cost Reduction: Enables cost-effective AI chip mass production High Security SRAM (On-chip Buffer: Near-compute Acceleration) HBM ( On - package Stack: High Bandwidth Access) DRAM (Off-chip DDR: Main System Memory) CXL Memory (System Fabric: Shared & Pooled Memory) Embedded Memory Repair PUF - Based Solutions Storage (Non - volatile Flash: Model & Weight Storage) 7
Page 10
. eMemory Anti-Fuse OTP vs. e-Fuse Anti-Fuse OTP (NeoFuse) e-Fuse Blown Fuse Blown Fuse Display Driver PMIC Sensor IC Camera MCU Multi-Media Automotive RFID Tag DRAM Connectivity Physically Visible: Vulnerable to Reverse Engineering Physically Invisible: Resistant to Physical Attacks xxx Arm RSS (Runtime Security Subsystem) Endorsement • Field-Programmable RSS Support: Enables secure storage of confidential code and data within the Runtime Security Subsystem. • High-Density Efficiency: Optimizes area for large arrays with seamless, low-overhead PUF integration. 8
Page 11
. eMemory e-Fuse Bottlenecks Area Overhead Mandatory SRAM buffering doubles the memory footprint due to read limitations. Advanced-Node SoCs Multiple e-Fuse blocks Diverse functional needs in advanced-node SoCs (e.g., ROM code, key storage) drive the mandatory use of multiple e- Fuse blocks. Design Complexity Scattered multiple e-Fuse block layouts trigger severe routing and power grid challenges. 9
Page 12
. eMemory ◼ eMemory’s OTP outperforms e-Fuse in area efficiency beyond 4K×8 densities. OTP Area Efficiency Item e-Fuse Solution OTP Solution OTP Advantages Number of Macros 16 Macros 1 Macro Single-macro simplicity Total Area ~1.92 mm² 0.33 mm² >80% Area reduction Additional SRAM Required Not required Zero buffer SRAM requirement Design Effort High (Scattered) Low (Centralized) Simplified layout & routing Total Area: 1.92 mm2 (excluding SRAM) Total Area: 0.33 mm2 16 × 2K×8 e-Fuse 1 × 32K×8 OTPExample: 32K x 8 Density 10
Page 13
. eMemory Registered IPs at TSMC 0 100 200 300 400 500 600 700 800 900 1000 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 3nm 5 - 4nm 7 - 6nm 16 - 12nm 28 - 22nm 45 - 40nm 65 - 55nm 90 - 80nm 0.13 - 0.11um 0.18 - 0.14um 0.25 - 0.2um 0.35 - 0.3um > 0.35um ◼ eMemory integrates widely across TSMC process nodes with over 850 registered IPs to enable broad customer adoption. IP Portfolio Trend (Unit: # of IPs) 11
Page 14
. eMemory 0 400 800 1,200 1,600 2,000 2,400 2,800 < 2005 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 3nm 5 - 4nm 7 - 6nm 16 - 12nm 28 - 22nm 45 - 40nm 65 - 55nm 90 - 80nm 0.13 - 0.11um 0.18 - 0.14um 0.25 - 0.2um 0.35 - 0.3um > 0.35um ◼ eMemory secures continuous success with over 2,600 new tape-outs (NTOs) across all leading-edge and mature process nodes. New T ape-Outs at TSMC New Tape-out Trend (Unit: # of tape-outs) 12
Page 15
. eMemory 0 5 10 15 20 25 30 35 < 2005 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 7 - 6nm 16 - 12nm 28 - 22nm 45 - 40nm 65 - 55nm 90 - 80nm 0.13 - 0.11um 0.18 - 0.14um 0.25 - 0.2um 0.35 - 0.3um > 0.35um Wafer Shipment at TSMC ◼ eMemory translates over 25M wafer shipments (8″-equivalent) into recurring royalty revenue with long-term visibility. Wafer Shipment Trend (Unit: M Wafers) 13
Page 16
. eMemory Accumulated Advanced-Node Licensed NTOs Leading-Edge Nodes (3nm–7nm) Mainstream Advanced Nodes (12nm/16nm) ◼ eMemory secures future growth with over 150 advanced-node tape-out licenses, building a high-value royalty pipeline driven by increasing adoption. 70 TOTAL TAPE-OUTS 88 TOTAL TAPE-OUTS 21 11 8 4 3 23 FPGA CPU/GPU/DPU SSD Controller Retimer ADAS Others 16 14 11 6 5 36 SoC Ethernet IC SSD Controller DDI ASIC Others 14
Page 17
. eMemory NTO Revenue (USD) Year NeoBit NeoFuse PUF-Based NeoBit NeoFuse PUF-Based 2002 3 2003 29 2004 40 2005 68 $ 4,217,380 2006 133 $ 6,202,270 2007 220 $ 9,402,479 2008 253 $ 12,896,211 2009 268 $ 11,695,587 2010 284 $ 15,873,331 2011 254 $ 15,399,098 2012 270 $ 19,620,768 2013 363 1 $ 25,436,669 $ 382,084 2014 371 3 $ 31,831,985 $ 328,787 2015 311 11 $ 30,943,426 $ 1,080,373 2016 270 28 $ 30,247,340 $ 3,636,142 2017 257 61 $ 34,619,653 $ 5,238,351 2018 253 86 1 $ 31,834,860 $ 10,773,223 $ 85,000 2019 226 109 2 $ 27,602,332 $ 14,466,279 $ 195,000 2020 248 182 3 $ 30,378,346 $ 26,437,660 $ 434,998 2021 252 259 6 $ 32,367,560 $ 44,011,223 $ 1,160,702 2022 264 231 33 $ 35,327,060 $ 63,762,480 $ 4,207,348 2023 226 241 29 $ 23,251,721 $ 64,276,058 $ 4,375,409 2024 266 270 32 $ 25,952,137 $ 71,649,123 $ 5,279,985 2025 253 248 54 $ 27,312,244 $ 78,122,682 $ 7,645,293 Total 5,382 1,730 160 $ 482,412,457 $ 384,164,465 $ 23,383,735 T ape-outs and Revenue by T echnology *Revenue includes both licensing and royalty 17
Page 18
. eMemory Hardware Root of Trust (HRoT) Software Security Stack - Core Function: Dynamic adaptation to new threats - Key Attribute: Continuous evolution Hardware Root of Trust - Core Function: Foundational trust for software - Key Attribute: Immutable permanence ◼ eMemory provides the foundational Hardware Root of Trust that secures the entire software stack throughout the chip's lifespan. 18
Page 19
. eMemory Next Computing: Confidential Computing ◼ Protect data in the Virtual Memory of Multi-Core CPUs ◼ CPU Cores and Virtual Memory have unique corresponding tag numbers ◼ Tag numbers are internally randomly generated by PUFcc (Crypto Coprocessor IP) Virtual Memory CPU Cores Core 1 Core 2 Core 3 Core N Realm 1 Realm 2 Realm 3 Realm N PUFcc Generated Tags … … Tag 1 Tag 2 Tag 3 Tag N Tag 1 Tag 2 Tag 3 Tag N Virtual Boundaries 19
Page 20
. eMemory ◼ eMemory drives security IP adoption by collaborating with leading foundry, processor, and cloud service providers. Security Business Development Foundry Platforms CPU Partners Cloud Service Providers (CSPs) TSMC, Intel, UMC, GF, etc. - Technology Licensing: Providing security IPs to leading global foundries. - Co-marketing Activities: Reaching diverse customer bases through joint promotional efforts. Arm, RISC-V, Cadence, etc. - System Integration: Addressing SoC customer needs for pre-integrated CPU and security subsystems. - Architectural Alignment: Collaborating with major processor providers like Arm and RISC-V. Microsoft, Meta, Google, Amazon, etc. - Hardware-to-Cloud Security: Working with CSPs on embedded security requirements at the chip level. - Root of Trust Solutions: Developing foundational security for systems like AWS, Meta, and Azure. 20
Page 21
. eMemory Standards Drive Hardware-Based Security IoT Data Center Using asymmetric public/private key encryption technology and device ID to achieve fast and secure access to the network. Driving an open standard for silicon root of trust. 21
Page 22
. eMemory Caliptra HRoT 1.0 ◼ eMemory’s RoT IP is fully ready to meet the hardware security requirements of the Caliptra specification. Caliptra Hardware Root of Trust (RoT) Caliptra RoT 1.0 eMemory IP Portfolio OTP PUF TRNG Crypto- processors Cryptography (PQC) Project Start Sep-21 Mar-24 Caliptra 1.0 Oct-24 Caliptra 2.0 (+PQC) Caliptra RoT 2.0 Caliptra-compliant IPs are designed to be integrated into a wide range of high-performance Data Center and Edge components: • Compute: CPUs, GPUs (Accelerators) • Storage: SSD Controllers • Networking: NICs (Network Interface Cards), SmartNICs, DPU • Custom Silicon: ASICs, SoCs Core Security Capabilities: • Unique Chip Identity • Secure Attestation • Secure Boot 22
Page 23
. eMemory Caliptra Drives Broader RoTAdoption Source: OCP EMEA Summit 2026 (Composable Security Architecture Episode 4: Bringing Together Platform Ingredients) ◼ Caliptra is driving broader RoT adoption across data center infrastructure, creating new opportunities for eMemory's RoT IP. VRs Debug Hardware CPLDs RoT for Attestation (TPM), Update, Recovery BMC CPU Firmware update/recovery boundary BMC/AMC Accelerators (GPU, TPU) Networking (NIC, TPU interconnect) RoT for Attestation (TPM), Storage TPM Storage devices OCP L.O.C.K Current Caliptra Internal RoT Deployment External RoT Integration Opportunity 23
Page 24
. eMemory Post- processing Conventional TRNG PUFtrng True Random Number Generator (TRNG) ◼ eMemory’s PUFtrng delivers 100x faster performance and superior entropy quality via PUF-based conditioning algorithms. Dynamic Entropy (Ring Oscillator) True Random Numbers Random Output Entropy Source Data Processing ➢ Low throughput random bits ➢ Slower Dynamic Entropy (Ring Oscillator) Static Entropy (PUF) Entropy Refine Engine True Random Numbers ➢ High throughput random bits ➢ 100x Faster 24
Page 25
. eMemory Post-Quantum Cryptography (PQC) Aug-23 Aug-24 NIST First Set of PQC Algorithms Standardized ◼ eMemory provides NIST-compliant hardware foundations to secure data against future quantum computing threats. PQC Migration Factsheet Released The Open PQC Standardization Project Launched Dec-16 Mar-26 Major CSP’s 2029 Q-Day Timeline Accelerated Quantum Threat: Conventional RSA and ECC encryption are vulnerable to future Shor’s algorithm attacks by quantum computers. NIST Standards: Official FIPS 203/204/205 and SP 800-208 define the mandatory PQC baseline for global industries. eMemory Achievements: Our PUFPQC attains full NIST coverage, securing the chain of trust from physical PUF to PQC algorithms. 25
Page 26
. eMemory eMemory for AI Servers and Edge Devices AI Servers + Memory RepairA Root of Trust provides: 1. Key storage/generation 2. Cryptographic processing to protect AI models, input data and output results 3. Confidential Computing B OTP needed for trimming analog circuits in Sensors and Actuators C NeoFlash to replace conventional eFlash for a much lower cost D 26
Page 27
. eMemory 27 eMemory enables High-Yielding SRAM Stored in eMemory OTP / eFuse ① Obtains location of bad memory cell ④ Replace and “switch” with bad memory cell ② Stores location of bad memory cell ③ Takes redundant memory column to replace column with bad cell Redundant ArrayMemory Array X : Bad Cell Smaller OTP size compared to eFuse: eFuse NeoFuse 64Kb ~0.1mm264Kb >1mm2 4Kb <0.1mm2 ! ! Repair needs 16~256Kb OTP! ◼ eMemory’s OTP enables high-density SRAM Repair, addressing scaling challenges at advanced nodes.
Page 28
. eMemory eMemory and Siemens: Partnering for Success eMemory provides OTP with interface for Siemens MBIST: • Tessent provides memory BISR functions with BIST and BIRA • NeoFuse OTP provides defect-free OTP using BIRA, BISR and adapter to Tessent • New MBISR: Tessent MBISR + NeoFuse, scann ing defective SRAM by word/column and loggin g to the OTP BIST = Built-in Self Test BIRA = Built-In Redundancy Analysis BISR = Memory Built-in Self Repair Siemens Tessent RAM FuseBox eMemory NeoFuse BIRA BIST Main Array Repair Row/ColumnBISR 1. Compact 2. Flexible 3. Robust 28
Page 29
. eMemory NeoPUF-based HSM Edge Server NeoPUF-based Crypto Engine Accelerator NeoPUF-based HSM Edge Server NeoPUF-based Secure Element Chip (PUFse) NeoPUF-based Security IPs ◼ eMemory embeds a physical unclonable root to secure hardware security module (HSM) infrastructure against hardware tampering and insider threats. 29
Page 30
. eMemory ◼ eMemory extends the physical root of trust to software platforms, enabling automated security provisioning for service workflows. NeoPUF-Based Hardware Security as a Service PUF-based FIDO Bio-MFA Client-Side Devices Smart Card SaaS Application Layer 30
Page 31
. eMemory Create a unique and unclonable hardware identity for every chip Establish a hardware root-of-trust, enabling secure key generation and device authentication Transform drones, radios, and satellites into trusted and traceable elements of the mission system NeoPUF Safeguards National Security ◼ eMemory establishes a non-replicable hardware identity to protect mission-critical defense supply chains. 31
Page 32
. eMemory Device Level System Level Supply Chain Level Device Level: Establishes Hardware Root -of-Trust • Device Authentication & Identification • Secure Key Generation Supply Chain Level: Enforces Global Traceability • Anti-Counterfeiting for Military Electronics • Supply Chain Security System Level: Guarantees Operational Integrity • Secure Boot & Firmware Integrity • IoT & Sensor Network Security ◼ eMemory deploys multi-level hardware security to ensure operational integrity from devices to global supply chains. NeoPUF Authenticates Defense Applications 32
Page 33
. eMemory Establishing an unforgeable identity for every chip, creating the ultimate foundation for zero- trust security. NeoPUF – The Holy Grail of Security Quantum-Proof Security: PUF based HSM Edge Server for PQC Migration Transforming hardware security into a scalable service, protecting critical data and infrastructure from cloud to edge. Chiplet Supply Chain Secured by NeoPUF Extending trust boundaries to secure the future of heterogeneous computing and integration. Click on the image to watch the video. Click on the image to watch the video. Click on the image to watch the video. NeoPUF: The Hardware Trust Anchor Powering Tomorrow’s Defense Systems Powering the trusted core of next-generation defense security. Click on the image to watch the video. 一張含有 文字,多媒體軟體,軟體,繪圖軟體 的圖片AI產生的內容可能不正確 。 eMemory Video Insight: Security in Action 33
Page 34
Thank You for your time. For more information, please visit: eMemory Website: https://www.ememory.com.tw/ PUFsecurity Website: https://www.pufsecurity.com/