Greetings. Welcome to the Aehr Test Systems fiscal 2025 third quarter financial results call. At this time, all participants are in a listen-only mode. A Q&A session will follow the formal presentation. If anyone should require operator assistance during the conference, please press star zero on your telephone keypad. Please note this conference is being recorded. I will now turn the conference over to your host, Jim Byers of Pondel Wilkinson Investor Relations. You may begin. Thank you, Operator. Good afternoon and welcome to Aehr Test Systems' third quarter fiscal 2025 financial results conference call. With me on today's call are Aehr Test Systems' President and Chief Executive Officer Gayn Erickson and Chief Financial Officer Chris Siu. Before I turn the call over to Gayn and Chris, I'd like to cover a few quick items. This afternoon, after market close, Aehr Test issued a press release announcing its third quarter fiscal 2025 results. That release is available on the company's website at aehr.com. This call is being broadcast live over the Internet for all interested parties, and the webcast will be archived on the Investor Relations page of the Aehr website. I'd like to remind everyone that on today's call, management will be making forward-looking statements today that are based on current information and estimates and are subject to a number of risks and uncertainties that could cause actual results to differ materially from those in the forward-looking statements. These factors that may cause results to differ materially from the forward-looking statements are discussed in the company's most recent periodic and current reports filed with the SEC. These forward-looking statements, including guidance and other issues, are only valid as of this date, and Aehr Test Systems undertakes no obligation to update the forward-looking statements. Now I'd like to turn the conference call over to Gayn Erickson, President and CEO. Thanks, Jim. Good afternoon, everyone, and welcome to our third quarter fiscal 2025 earnings conference call. Thanks for joining us today. I'll begin with a few opening comments, and then I'd like to spend some time discussing tariffs and Aehr's perspective on the near and long-term implications, as this topic is obviously on everyone's mind. We received many inquiries seeking answers regarding this matter. I'll then provide a brief overview of the quarter's key highlights and share updates on the primary markets that Aehr targets for semiconductor testing and burn-in, including the significant progress we've made so far this year in new markets. After that, Chris will deliver a detailed review of our financial performance, and finally, we'll open up the floor to your questions. We're pleased to report third quarter revenue growth in solid bookings and backlog, and that we exceeded the street financial forecast consensus for both revenue and bottom line for the quarter. We're particularly excited by the significant progress we've made expanding into additional key markets and unlocking new opportunities to attract customers and drive revenue growth. Recent wins have helped us meaningfully diversify beyond silicon carbide and into high-growth markets like AI processors with our industry-leading wafer-level and package-part test and burn-in solutions. Okay, so tariffs. Currently, it appears that the actions and announcements from the U.S. administration regarding tariffs are dominating the news cycle. At this time, we do not believe that the impact of the tariff announcements made by the U.S. administration last week will significantly affect Aehr directly. However, we're looking at the near-term secondary effects on our current and potential new customers, along with the uncertainty this quarter regarding possible pauses or delays in customer orders, shipments, or supply chain delivery delays or disruptions. Our immediate goal is to assess the impact on a customer-by-customer basis and communicate this to them quickly to remove any uncertainty or risk so that they do not slow down or delay any orders. We already have on hand the material needed for shipments of our wafer-level burn-in and package-part burn-in systems over the next couple of quarters. For wafer-level burn-in systems, it's much longer than that. For consumables such as our wafer packs for wafer-level burn-in and burn-in boards and modules for our package-part burn-in systems, these are quick-turn items with material purchased and built to order. We're already redirecting these materials and looking to dropship finished goods from our subcontractors, as well as shifting assembly and test of our wafer packs to one of our international locations as needed to minimize tariffs and avoid any possible supply chain disruption. We also have wafer pack aligners on hand to buffer us from any tariff noise for several quarters. For the high-power probers for our FOX- CP for our hard-disk drive customer, the probers come from Japan, and we may look to dropship directly from Japan to this customer so as to not even have to consider the U.S. tariff implication. However, give it a couple of days, and we may have a new tariff number with Japan, or it may be zero. I provide this detail to help our customers and shareholders understand that we do have a robust supply chain and have put thought into the resiliency of our shipments for customers so they can count on us. Again, we do not believe the impact on margins or demand will be significant for Aehr or on customer demand over time, but the challenge is not being able to control near-term secondary effects on our current and potential new customers, such as possible near-term delays in customer orders or requested delivery dates, given the unknown potential tariff implications on their products or supply chain. I'll be happy to answer any additional questions on tariffs as best I can in the Q&A section. Okay, now on to running our business and to meet the needs of our customers and shareholders and stakeholders. We have been laser-focused on the initiatives we set out to expand our total addressable markets, diversify our customer base, and develop new products, capabilities, and capacity to grow the business moving forward. I'll cover this in more detail, but we believe that the total available market for these target wafer-level and package-part burn-in markets we're addressing this year, plus the added flash memory wafer-level burn-in that we're working on, has an addressable market of over $500 million in systems alone, plus another $500 million in consumables and wafer and device handling equipment by 2027. We're excited by the significant progress we've made this year in expanding into new key markets and unlocking new opportunities to attract customers and drive revenue growth, and particularly in diversifying our markets and customers beyond our revenue concentration last fiscal year with silicon carbide wafer-level burn-in. Silicon carbide wafer-level burn-in accounted for over 90% of our business in fiscal 2024, while this year it's tracking to less than 40%, with artificial intelligence processors burn-in representing over 35% of our business in just the first year. For the third quarter, we had four customers representing over 10% of revenue, and three of these are new customers/markets for Aehr: wafer-level burn-in for AI processors, package-part burn-in for qualification and ongoing process monitoring of AI processors, and wafer-level burn-in of gallium nitride semiconductors. If you look at bookings, yet another customer and market, hard-disk drive components, accounted for over 15% of bookings. We're very excited about our expansion into new customers and markets, while at the same time, we believe we're well-positioned to continue to grow our business in the silicon carbide wafer-level burn-in market. For AI processors during the quarter, we qualified, received orders for, and shipped the world's first wafer-level burn-in systems specifically designed for AI processors. Our new high-power FOX- XP wafer-level burn-in system can test up to nine 300 mm AI processor wafers simultaneously. This new customer ordered multiple XP systems and sets of Aehr proprietary wafer-packed full wafer contactors for installation at their OSAT test house, which is the offshore or outsourced assembly and test house. Aehr has worked with this OSAT test house for many years, including working on wafer-level burn-in in silicon photonics devices and optical sensors on our FOX systems and on package-part burn-in of AI processors and ASICs on our Sonoma ultra-high-powered test and burn-in systems. Aehr is the only company on the market that offers both a wafer-level burn-in system as well as a package-part burn-in system for both qualification test and production screening and burn-in of AI processors. Another new market for Aehr is adding the production side of package-part burn-in for AI processors in addition to the processor qualification burn-in. We've now shipped multiple Sonoma production burn-in systems this year to a world-leading hyperscaler for production package-part burn-in of their AI application-specific processors and expect to complete the installations on this initial order by the end of the current quarter. We've also successfully integrated the Sonoma system from the acquisition of Intel Technology last August into Aehr's engineering and manufacturing operations, which has enabled us to scale our output to two to three times the previous record shipment volume. In addition to AI-related orders and installations for wafer-level burn-in and package-part burn-in this quarter, Aehr achieved several other key milestones. We expanded into production wafer-level burn-in for gallium nitride power semiconductors. We secured our first high-volume production orders for the new wafer-level burn-in in hard-disk drives. We completed production qualification of our new high-power multi-wafer system for wafer-level burn-in of silicon photonics devices used in co-package optics and optical I/O devices, and we made significant progress on proof-of-concept work with a leading flash memory supplier on a new wafer-level burn-in system for high-volume production of next-generation flash memory devices. Let me expand on each of these for just a moment and then come back to silicon carbide. I believe our most significant achievement so far this year is the successful validation of our new high-power FOX- XP wafer-level burn-in system, which can test up to nine 300 mm wafers simultaneously with a power output of up to 3,500 W per wafer. The key lies in delivering thousands of amps of current to and from each wafer while maintaining precise voltages and thermally controlling these wafers to prevent thermal runaway. We achieve this by running bidirectional logic and memory test patterns on each device, ensuring accurate burning conditions and traceability, including reading device IDs and on-wafer temperature sensors for every device. This customer has told us that they're very excited about our system and that no other product on the market has the capability or capacity to test their wafers like our system. They've ordered multiple FOX- XP systems and sets of Aehr proprietary wafer-packed contactors and have already completed the first system installation and will complete the installations of all of the systems from this first order this quarter at the customer's OSAT, one of the largest OSATs in the world. As I mentioned, Aehr has worked with this OSAT test house for many years, including working on wafer-level burn-in silicon photonics devices and optical sensors on our FOX systems and on package-part burn-in of AI processors and ASICs on our Sonoma ultra-high-powered test and burn-in systems. We believe that allowing customers to test and burn-in their processors at the wafer level before packaging them into multi-chip arrangements with other processors and memory adds significant value. We're confident that we're not only years ahead in this technology, but we also hold critical IP and patents around the world to safeguard our wafer-level burn-in technology and solutions. The cloud accelerator semiconductor market is experiencing explosive growth. UBS estimates that revenues in 2024 will exceed $120 billion, and the market is growing at a CAGR of over 30%. These devices are currently burned-in almost entirely at the system level, where a failed device during burn-in is significantly more expensive than at the wafer level. It is not just the cost of the advanced packaging that matters, but also the expense of co-packaged memory, as well as customers shifting to multiple processors within the same package. An annual capital test budget of 2%-5% of revenue is typical in the semiconductor testing industry, implying a budget of $3 billion-$9 billion for overall testing in 2024. The potential for a solution that can do test and burn-in screening of devices while still in wafer form is remarkable, and Aehr is the first and only company in the world to demonstrate and successfully achieve this for production burn-in at the wafer level. I'm very proud of our team for this achievement with AI wafer-level burn-in. Simultaneously, the finance, R&D, and manufacturing teams did an incredible job integrating Intel technology into Aehr. Within months, they ramped up production to levels that Intel may never have been able to reach to meet the demand from AI processor companies for the qualification and production of their devices. Aehr has shipped more Intel package-part burn-in systems in the past nine months than Intel had shipped in the previous three years. Great job to the combined team. Let's keep it up as we ramp these new customers into volume production with these systems. We're also already developing multiple enhancements to increase power, cooling, parallelism, and add automation to meet the needs of the AI processor market in the future. I'm very pleased with the customer feedback on these enhancements so far. We also shipped our first FOX-XP high-power multi-wafer production system with high voltage to a world-leading gallium nitride power semiconductor supplier this quarter. The system is installed and configured with our fully automated integrated wafer pack aligner, which can test 6 in and 8 in wafers and can even be configured for future 12 in or 300 mm GAN wafers. While the system is installed for volume production of GAN devices, it is also configured to test silicon carbide wafers in the same system by simply changing the wafer pack full wafer contactors. Nitride is a new and exciting semiconductor technology with high-value applications such as automotive power conversion, solar inverters, and solid-state transformers and breakers. We're thrilled to have been selected as the production solution for this company, which is one of the largest suppliers of power and automotive qualified semiconductors in the world. Another exciting market opportunity we're making significant progress on is the hard-disk drive market. This quarter, we received orders for multiple FOX- CP single-wafer production test and burn-in systems with an integrated high-power wafer prober for the burn-in and stabilization of new devices and hard-disk drive heads. We're excited to finally start this production ramp after several years of working with this company on qualification and process development. This order arrived later than we expected. However, the customer is requesting shipment of all the systems as soon as possible and has already requested a forecast for when we can ship additional systems. Lastly, I want to update you on our flash memory proof-of-concept project that we've been working on this year. As noted in earlier calls, we're collaborating with one of the world's leaders in flash memory to demonstrate the capability and cost-effectiveness of our FOX-XP platform for high-volume production testing and burn-in of flash memory wafers. Our goal has been to demonstrate this over the next quarter, and we're on track. We're setting up the test cell and new wafer packs with a high-density fine-pitch probe head during the upcoming month. This is very exciting as we believe Aehr has the ability to successfully demonstrate how we can achieve a high-density, high-power, and fully automated test cell, enabling us to advance to the next development phase. That next phase involves collaborating to develop a next-generation test system specifically tailored to meet this customer's needs and future requirements. Stay tuned for more updates on this demonstration and the potential for the NAND wafer-level testing and burn-in market. To provide perspective, the NAND market in 2025 is expected to exceed $80 billion, according to Yale Group. Again, using the 2%-5% rule of thumb for the budget for overall testing of semiconductor devices annually translates to a capital and expense budget in 2025 of between $1.6 billion and $4.2 billion. Another way of looking at it is that a 1% yield improvement on the $80 billion market amounts to $800 million. New technologies in NAND are driving new requirements for wafer-level burn-in to address the manufacturing and negative yield implications of testing these NAND devices in package or system-level test. It's easy to see why the potential for the market for wafer-level burn-in for NAND is substantial. Okay, now let me close with silicon carbide wafer-level burn-in market. The silicon carbide market continues to be a large opportunity for Aehr, and as I noted earlier, we believe we're well-positioned to continue to grow our business in this market. Recently, we've noticed some signs of improvement in the utilization rates of our installed base of wafer-level burn-in systems for silicon carbide. Demand for silicon carbide remains significantly driven by electric vehicles and has even further strengthened its presence in the EV market due to lower prices and better supply availability. Battery electric vehicles are still expected to be over 30% of all vehicles shipped in 2030 worldwide. Simultaneously, silicon carbide devices are gaining traction in other markets such as power infrastructure, solar, and various industrial applications. According to market research firm Yale Group, despite a temporary slowdown in battery electric vehicle shipments, the silicon carbide market continues on a robust long-term growth trajectory. Yale projects that the power silicon carbide market will exceed $10 billion by 2029, driven by a strong rebound expected in 2026, along with a compound annual growth rate of nearly 20% from 2024- 2029. In response to this growing demand, we've expanded our wafer-level burn-in offering for silicon carbide to support high-voltage testing across up to 18 wafers on a single system, doubling the capacity of our industry-leading nine-wafer FOX-XP system. We've already received our first order for this 18-wafer high-voltage system as an upgrade to a customer's existing FOX-XP configuration. This enhancement further strengthens our technical and cost advantages for silicon carbide testing and is also highly applicable to high-volume production of GaN devices, an important capability for customers working on both types of wide-band gap compound semiconductors. Now, here's some more details I mentioned, I would say, on our available market assumptions. According to market researcher Verified Market Research, which aligns with Aehr internal forecast based on customer and other data from Yale, UBS, and other market forecasters, the burn-in test systems market for semiconductors is estimated to grow from approximately $750 million in 2024 to over $1.2 billion in 2030, a CAGR of 9%. This is for systems alone, not the consumables such as our wafer packs or BIBs, or handling equipment such as our aligners, probers, or auto loaders for package-part burn-in. Historically, semiconductor burn-in consumables are up to three times the annual spending on burn-in systems. By 2027, the burn-in systems TAM is forecasted to be $1 billion, and we estimate that just for the new systems purchased in 2026 and 2027, the consumables and handling equipment are at least another $1 billion. In this TAM are AI and high-performance computing processors, other microprocessors, DRAM, flash, optical, and compound semis. DRAM and MPUs are interesting in that the top MPU company and one of the top three DRAM companies make their own burn-in equipment, so this is not included in the system TAMs. With the introduction of our new products in compound semi, optical, both wafer-level and package for AI and high-performance computing processors, and our target to enter the flash wafer-level burn-in market, Aehr addresses over half of this TAM. We believe that we can address over $500 million of this TAM in 2027 for systems alone, and since Aehr provides turnkey solutions for handling and consumables, we address another $500 million annually for a total of a billion-dollar TAM. The largest portion of this is clearly the AI market, followed by the flash market, with GaN and SiC, silicon photonics, and hard-disk drive optical devices rounding out the total addressable market. Obviously, we're very excited about all of these opportunities for growth. Now, let me close it out and hand it over to Chris. Looking ahead with our $45 million in revenue and $22 million in backlog to date this fiscal year, our customer forecasts, and our success in adding new markets and customers, we feel very good about our business. We've already surpassed $66 million in combined revenue and orders this fiscal year. Currently, we do not believe that the impact of the tariff announcements made by the U.S. administration this week will significantly affect Aehr directly. However, considering the secondary effects on our current and potential new customers, along with the uncertainty this quarter regarding possible delays or pauses in customer orders, shipments, or supply chain delivery delays or impact, we're temporarily withdrawing our guidance for this quarter/fiscal year, which ends May 30, and we'll reassess our guidance policy as clarity develops. We're encouraged by the increasing number of engagements with both current and potential customers, as well as the long-term growth potential across our diverse target markets. Our strategic expansion in the high-growth sectors, including artificial intelligence processors, gallium nitride power semiconductors, data storage devices, silicon photonics integrated circuits, and flash memory, opens up new opportunities to attract customers and drive revenue growth. With that, let me turn it over to Chris, and then we'll open up the line for questions. Thank you, Gayn. Before we view our financial results, I would like to provide an update on the integration of our Intel acquisition, which closed last July. Our plan to consolidate personnel and manufacturing into Aehr's Fremont facility is progressing well, and we remain on track to complete the integration by the end of this fiscal year on May 30. As part of this effort, we have upgraded water and power systems and added new clean rooms to our remodeled Fremont headquarters to ensure the infrastructure supports the needs of both organizations. We'll be shutting down the Intel facility no later than the first quarter of fiscal 2026. Since the acquisition, Aehr has committed significant financial and human resources to successfully integrate Intel into our operations. We have completed the migration of Intel's financial, HR, and manufacturing functions into Aehr systems. In addition, we have finalized the transfer and documentation of all product designs, source code, and work instructions for assembly and test into Aehr's release processes. I want to extend my sincere thanks to both teams for the dedication and outstanding execution throughout this integration. Turning to our Q3 performance, which included a full quarter of the financial results from the Intel acquisition, our Q3 results exceeded the analyst consensus on both the top and bottom lines. While we faced a challenging environment marked by continued softness in the silicon carbide power semiconductor market, we were encouraged by our success in penetrating the artificial intelligence market, with AI processors burn-in now representing over 35% of our business this year. During the third quarter, we had four customers representing over 10% of total revenue, and two of these customers are new customers that target the AI market. Revenue for the third quarter totaled $18.3 million, a 142% increase compared to the $7.6 million in Q3 last year. This significant year-over-year revenue growth was driven primarily by the shipments of our new high-power FOX-XP solution for wafer-level production tests and burn-in of AI processors delivered to our first AI processor customer, which we announced in December. In addition, we're pleased with the significant progress we've made integrating products from our acquisition of Intel into our product portfolio to address the AI market opportunities. System sales from our Sonoma, Tahoe, and ACKO package-part burn-in products made a strong contribution to our third-quarter revenue. We believe our strategy to broaden Aehr's offerings and diversify beyond silicon carbide applications is beginning to show positive results both operationally and financially. Wafer pack revenues were $5.9 million, accounting for 32% of our total revenue in the third quarter, a decrease from 63% in the same period last year. The company recognized bookings of $24.1 million in the third quarter of fiscal 2025, compared to $9.2 million in the second quarter of fiscal 2025. Our backlog at the end of the quarter was $18.2 million. Since the end of the third quarter of fiscal 2025, we have received $3.6 million in additional bookings. With this recent bookings, our effective backlog now stands at $21.8 million. Non-GAAP gross margin for the third quarter was 42.7%, compared to 42.5% in the same period last year. The overall change in gross margin was flat, primarily due to a much higher overall revenue level than in Q3 last year, offset by a less favorable product mix and one-time items. Even though our revenue in the third quarter was much higher than that in the same period last year, our non-GAAP gross margin was lower than expected due to certain one-time charges to our cost of revenue. After we upgraded our ERP from our legacy system to Oracle NetSuite, our new ERP allowed us to account for standard costs in inventory more precisely and revise certain accounting estimates, which resulted in a one-time charge in the third quarter. Additionally, we incurred high manufacturing overhead due to underabsorption, as we had lower utilization of our manufacturing capacity due to the renovation of our Fremont manufacturing facilities. Non-GAAP operating expenses in the third quarter were $6.3 million, reflecting a 34% increase from the $4.7 million in Q3 last year. This year-over-year rise is primarily attributed to the inclusion of Intel's operating expenses in our financial results, along with higher legal and professional service fees. We anticipate incurring additional legal expenses in the upcoming quarters, as we strive to protect our intellectual property rights in China and defend against the class action and derivative complaints in the U.S., which we believe lack merits. Non-GAAP net income for the third quarter, excluding the impact of stock-based compensation, acquisition-related costs, the fair value adjustment to inventory related to the acquisition, amortization of intangible assets, and the accelerated severance benefits paid to an executive who passed away unexpectedly in December, was $2.0 million or $0.07 per diluted share. This compares to a non-GAAP net loss of $888,000 or negative $0.03 per diluted share in the third quarter of fiscal 2024. Turning to our balance sheet, at the end of Q3, our cash, cash equivalents, and restricted cash totaled $31.4 million, down from $35.2 million at the end of Q2. During the quarter, we used $1.6 million in operating cash flows primarily to pay our suppliers and service providers. We have no debt and continue to invest excess cash in money market funds. In the third quarter, we earned $270,000 in interest income. As Gayn mentioned, considering the secondary effects of the tariff announcements on our recent and potential new customers, along with the uncertainty this quarter regarding possible pauses or delays in customer orders, shipments, or supply chain delivery delays, we are temporarily withdrawing our guidance for our current fiscal 2025 year ending May 30th, and we'll reassess our guidance policy as clarity develops. Looking ahead to fiscal 2026, we are encouraged by the growing number of engagements with both current and potential customers, as well as the long-term growth potential across our diverse target markets. Our strategic expansion into high-growth sectors, including artificial intelligence processors, gallium nitride power semiconductors, data storage devices, silicon photonics integrated circuits, and flash memory, opens new opportunities to attract customers and drive revenue growth. Lastly, looking at the investor relations calendar, Aehr Test will be participating in two investor conferences over the next couple of months. We will be meeting with investors at the Craig-Hallum Institutional Investor Conference, taking place in Minneapolis on May 28th, and we will be presenting and meeting with investors on June 3rd at the William Blair 45th Annual Growth Conference, taking place in Chicago. We hope to see some of you at these conferences. This concludes our prepared remarks. We're now ready to take your questions. Operator, please go ahead. Thank you. At this time, we will be conducting a Q&A session. If you would like to ask a question, please press star one on your telephone keypad. A confirmation tone will indicate your line is in the question queue. You may press star two if you would like to remove your question from the queue. For participants using speaker equipment, it may be necessary to pick up your handset before pressing the star keys. One moment, please, while we pull for questions. Once again, please press star one if you have a question or a comment. Our first question comes from Christian Schwab with Craig-Hallum. Please proceed. Hey, guys. This is Tyler on behalf of Christian. Thanks for letting us ask a couple of questions here. Maybe first to start on the tariffs and the uncertainty here, I guess, any color on maybe which end markets you are seeing maybe the most potential impact or most potential uncertainty being caused on the near term here? I think we certainly prepared lots of different things. That's a good question. No, I don't—it's not markets. Sometimes it's more customers and geographies, right? In this case, I'll give you one example. Our hard-distribution customer, okay, has systems that are going to be going to a location outside the U.S. It includes a prober. We basically worked with a supplier that developed a high-power prober specific for this requirement. Prober companies are out of Japan or Korea, basically, okay, without saying which one it was, okay? They both are currently subject to a tariff. If that prober landed in the port tomorrow, it's going to get hit by a tariff. If it lands Friday, it may not. I think people are like, "Well, let's wait and see what happens," I mean, because I don't think anybody believes that if you write a check for the tariff, you get it back necessarily. Now, having said that, we're also looking at tariff drawbacks, which is basically a process by which, historically, with duties, if we import something to assembly and then export it out, you can actually recover that up to 99% of it or so, although there are some people saying that the people that help you with that get a cut. We're working through that as well. In the meantime, I'm going to dropship the probers directly to that customer past the first one. The very first one is being impacted by, which is kind of the over/under, with respect to the end of our fiscal year because we're going to do some integration of it here. We may even have to relook at that. It's that sort of tactical thing. Give it a couple of days. We're, what, three days in? Chris and I were saying, "Could we have another week? Let things settle out before this call." Again, a lot of the material we have already on hand, it will never be subject to any tariffs, I guess, unless we ship it out to someone who then increases their tariffs. Last night, I went to bed thinking that Europe was going to come back and raise their tariffs. Today, they wake up and they say zero for zero. It's kind of hard to look at it. Honestly, I don't think anyone's so desperate to try and solve these things in the next couple of weeks either, if you look at just schedules. I think we can manage through this. Even then, we start looking at material in many cases because remember, our inbound material tariffs are on the material. We then, of course, have a markup or margin to ship it. A tax on the material of 10% is not a tax of the price. Does that make sense? We kind of walk through that. I would say that there's not a specific market. Obviously, China is its own challenge in that I think they came back and said it's 104% starting tomorrow. We actually have, if you specifically look at kind of risks related to China, just a couple of things. Aehr has basically had no revenue shipments into China for the last few years. That includes both our wafer-level stuff and the Intel products. We are not depending upon shipping a lot of revenue into China. That has not been the plan. If China comes back and says, "We're going to halt shipments," or, "We're going to double the tariffs," or whatever, it does not really affect us right now, okay? Similarly, we have been pretty happy and proud that we almost do nothing in China from a supply chain perspective. I have said that in previous calls. We actually have some things like blank printed circuit board fabs, but not the assembled ones. It is pretty simple, and we have secondary suppliers for that, just from a risk perspective. We continue to buy from them because the landing costs made more sense, but we also can supply it out of several other countries. We wake up and like, "Which country should we supply it from?" It's like, give it a day." There is a little bit of settling out on this. That, again, is not even so much of the cost implications to margins as potential supply chain risks. What if they put that in a crate, it is shipped over here, and it gets stuck in customs because people are trying to figure out what country it came from and on what day did it come in because that is the tariff it is applied to? We're actually doing things to try and avoid anything coming into the US for customs in the near term, not even so much for tariffs, just simply do not cluster, have it get cluttered up, and then you have it in the wrong place. We can redirect things. We have things we have supplied from material and subsistence from all over the world. They can dropship directly into a customer internationally, and we do not even have to worry about any of this stuff. We have the infrastructure. We have the ERP systems. We have the legal entities that we can do that. Candidly, we're kind of proud of that supply chain. I mean, with the China COVID thing, I think everybody had to take a look at it. We actually were also quite immune from anything during COVID, but this has been an important thing to tell your customers. What happens if such and such happens? We've said, "You're not going to miss a shipment. We're going to be okay," right? It is kind of an important thing to note so people understand it. At the same time, we can't answer everything. Remember, May 30th is, what, seven weeks away? I mean, we're like—as you know, plus or minus one system on ours can move the bar. That is why we just pulled the near-term guidance. I appreciate that. That is a bunch of really great colors. I guess following up on that, then giving those comments, uncertainty around additional orders and timing of when customers might demand shipments. You had $18 million in backlog exiting the quarter, $22 million effective since then. Would it be reasonable, or erring on the conservative side, at least reasonable to think that you probably won't even ship all of the backlog you currently have on hand in the quarter? Is that a great way to think about it? One of the keys is if we're going to say we're not going to give guidance, we can't really give guidance. Nevertheless, let me still answer that directly. For sure, some of that backlog is not going to ship this quarter because it's multiple systems for the hard-distributed guy. We were only planning to maybe ship one of those. We said that last quarter. The over/under right now is one, maybe a second one for this quarter, not all of them. Some of those are already planned for them. The interesting thing is we have multiple customer forecasts for things to ship this month or this quarter that they have not ordered yet. You are like, "Okay, is that going to happen? Would that happen that I can still turn that?" Some of it we have material on hand, and some of it is stuff that is inbound. I would love to tell you it is that simple. If it was, I would probably just give you a new guidance, but it is sort of there is kind of upside and downside to all of this. I apologize for not being really clear. I think the important thing is, okay, we miss it, we miss it by a little whatever, or it is going to be close. It might ship by the next week. That is the thing that can be very scary as a public company, right? If they're private, I wouldn't even worry about it. I'm only worried about the customers getting their shipments, getting to them on time. Plus or minus one day on May 30 is a big deal to us as a public company. This is more the things I'm talking about here, this is just timing stuff, we think, okay? This is more timing things. I don't think the customers that are already buying, they've taken, in some cases, six months to a year to qualify. I mean, if you look at the GaN customer, the hard-distributed customer, this AI customer, the package-part burn-in AI customer, we've worked with them for over a year. They're fully qualified. They're committed. Now the question is, how do we make sure that they can get the equipment on time with the least duties or tariffs at all possible, okay? All right. I appreciate that. That's great color. If you think of another one, Tyler, you can always come back too. Go ahead. What's the next question? Sorry. No, let's move on past the tariff. As we think about next year in growth, you've diversified your revenue nicely away from silicon carbide. Maybe at least rank order. It sounds like silicon carbide is expected to continue to recover. We would expect to see growth there, but maybe AI is going to be the primary growth driver as we look out the next year or two. Just any color kind of rank ordering where you expect to see the growth from your more diversified end markets. Yeah. I mean, we're feeling really good about next year. I mean, there definitely is evidence that silicon carbide will kind of get back to capital equipment growth and putting more capacity in place. We're also seeing a shift from low voltage gate to high voltage testing, something we've done by working with several of the OEMs, the actual EV suppliers for quality that they're driving to their customers, which drives them towards us, that even if they have equipment, they may need to upgrade it. That also turns into wafer pack revenue. We think we can see revenue from our current installed base in both wafer packs and system upgrades, but then also incremental capacity. There are still a few customers that effectively selected us, if you will, and haven't bought their first systems because they've delayed some of their fabs that Yale is saying they will start to turn on in 2026. 2026 is when they say it's calendar. My fiscal 2026 starts June. Some of that capacity may be second half, but we feel some of this already in our first half or so or second half of 2025. Our fiscal year has kind of messed people up. Let's see here. GaN, we're pretty excited about that. There's some—we have done a large number, I mean, a good number of designs that have been qualified into automotive industrial applications. They're now just going into production. We've kind of got our fingers crossed related to that around their capacity and their needs to grow. We're talking with several other customers. We've actually heard our silicon photonics customer is talking now about ramping this year. That's with the very high power. Remember, we upgraded their fleet to the extra high power system, which needs new wafer packs and needs new system upgrades. That's encouraging because of all the stuff that's finally going on around the silicon photonics side. I think we think that the package-part burn-in qual is going to continue to grow. There's a lot of new devices coming out with higher power that's going to drive demand. Burn-in, the production side of it. The production burn-in, we're seeing our first customer ramp. It's in a very visible OSAT. We're literally shipping all the systems. We finish it this quarter, and they start their first ramp. We think they'll need more systems. We're also working on some enhancements. I don't want to get ahead of myself here in too much public, but we're working on some automation and some very specific things in the capability to add to that package-part burn-in and have been communicating that to the customers and the OSATs right now. I'm very hopeful and encouraged by the feedback that could drive more and more production burn-in to our systems with full automation with the Sonoma line. Lastly, but honestly, maybe most impactful is what's going on with the wafer level. That first customer is expected to ramp. We already have inbounds from other people. People are really leaning in to understand what do they need to do, what testability modes do they need to add to their wafer, how can they do this? Because the implications of being able to weed out the failure of that processor before you stick it into a large package with co-packaged memory, optics, and other processors is huge. That could be some of the most exciting stuff that's going on. Flash memory, we've spent—actually, we're spending a significant amount of R&D money this year. We're spending our money, I say our as collectively as shareholders. It's a great investment. We're going to need to invest even more next year in developing the test solution to go in that. Maybe we could get some revenue at the end of the year, but this is really early 2027 is what we're thinking in terms of the timing. That's why I use those TAMs around 2027 to kind of capture at that point. We would hope to have flash memory revenue, wafer-level burn-in across more than hopefully several or more customers, package-part burn-in across several customers, silicon carbide hitting, GaN starting to ramp, and the hard disk drive just continuing to buy along with silicon photonics. That's great. All right. That's all for us. Thanks, Gayn. Okay. The next question comes from Jed Dorsheimer with William Blair. Please proceed. Hi. Thanks for taking my question. Gayn, I don't want to ask you a bunch of questions you don't want to answer. Just I guess first one, just on the balance sheet, I'm curious, AR, your accounts receivable jumped up quite a bit. Is that just from Incal? Is there a change in terms? Could you just talk about what was going on there? Because I saw that, positively, inventories actually came down while revenues grew. I'm just wondering about the receivables seem to jump out. I got a follow-up. Yeah. We also have a bill receivable in our receivable balance that we were able to recognize revenue, but cannot bill yet. I think by now we have sent out an invoice at this point. AR, it's called shipments towards the last month of the quarter. Not atypical of that. I think that was it. I think we may have had a special term with one of the customers with respect to billing at final shipment or something on the first tool, a couple of those things. I wouldn't read too much into it. Over time, and I want to be sensitive to this because we have customers listening as well. We do do down payments under most circumstances. Sometimes with short lead times and things like that, we will work with the customer. Billing them 30% and then two weeks later hitting them with the other one sometimes is not most optimum. We try and be balanced on it. In general, we want to make sure that customers have skin in the game when they're placing the orders on these systems. There is a little of that, but yeah, there are no flags, no nothing. There is nothing there. Okay. Just on that AI, on the processing side of things and burn-in, I was wondering if you could go through the value proposition in a little bit more granularity. What needs to be achieved for this? Has this gone from R&D to commercial level, or do you feel like there's still, even though the size and scale of the orders might be commercial size compared to that of silicon carbide for these customers, do you feel like it's progressed more that it's gone beyond in your—what are you looking at to get the determination that, okay, we're going to start ramping on this in a durable way? All right. Jed, I think I understand it. Let me try and answer it while repeating the question a little bit along the way. If the question is, is this sort of like an NPI prototype, like a trial run, and they haven't really worked that kind of thing? That's not the case. This customer, and we've alluded to it before, and we have to be somewhat sensitive to what's known publicly and what they've said. Yes, we have not identified who it is yet, okay? What we have said is that they were doing, which is very similar to a lot of other AI guys, they were doing this burn-in at what's known as system-level test, okay? This is very late in the process, basically damn near at the product side of things, okay? The problem with doing it at system-level test is that it's very late in the process, and any processing implications, etc., and you have to use a much more different and sophisticated piece of equipment or the equipment itself to burn itself in to actually find these failures. The other challenge is that in a system-level test, you often have this memory or this processor coexist. I'm going to be a little careful about too much detail on this because people are all trying to figure out, is it what kind of AI processor is it? We hope to come much more public with it. The customer has talked about doing that. It exists with other things: memories, infrastructure, heat sinks, power supplies, and all this. Burn-in, I know a lot of people understand, is what it sounds like. You basically are heating it up, and you're actually adding more power to it to stress the device to a point that it'll weed out infant mortality or weak devices. You do not want to break it, okay? The trick is to try and get it right to the edge to accelerate this stress test to weed out things in as short a time as possible, okay? Generally speaking, the more power you put in and the more heat you put in, the faster you can do it. If you put in too much power and too much heat, you wreck the part, right? It turns out each device has a different optimum spot. Flash memory is like 85 degrees. DRAM can be 105 degrees. A microprocessor is 125 degrees. Silicon carbide is 140 degrees. They are all at different numbers. If you put them all into the same package, and I am not saying you put silicon carbide into that package, okay? Let me throw in silicon photonics. There are actually two burning temperatures for it. You do one process at one temperature and one at the other for ideal. Now stick them all into a large package. What are you burning in that? It is a problem. If you burn it, if you were to put it in an oven and you burnt in the processor at 125, you could wreck the DRAM, okay? You certainly can't bring the processor to 140 degrees like you do the silicon photonics device. What you do is you bring it to the lowest common denominator, but here's another problem. That system is not designed to be run hot. The whole point is it's being run cold with big heat sinks and water cooling. Think of all the stuff that's going on in these racks. It's normally trying to run at 30 degrees, and I use centigrade. Sorry for everybody. A little bit more room temperature, right? That's what you were trying to run it at. When you burn it in, we're running it at 125 degrees centigrade, 25% more than boiling water, okay? You can't do that with a system. You would ruin everything. You'd ruin all the printed circuit boards. You'd wreck all the memory. The power supplies would all die. That's not good. You burn it in way lower temperature, maybe 60 degrees. If you do that, then the burning time is like 10 times longer. If you actually move it to the wafer level, I can burn in your memory right within a few degrees or 125 degrees and keep it from going in a thermal runaway. That minimizes the burning time. I perfectly optimize that. You take that device, and now when you put it in the system, it will not fail. It's a big deal. It's a really big deal. By the way, like on our package-part burn-in systems, which we have, one of my favorite things is I have a front row seat. On the Sonoma systems, we're testing these packages. We're testing the memory stacks in there and the processors and the chipsets. We have to actually test those at different conditions. It's a very interesting challenge, but it's way more effective if you can break it down and do it at the wafer level. Until now, no one has ever even imagined doing that. We now have the technology with the power, the power supplies, the capability, the JTAG and MBUS patterns and functionality and read and write capability to actually test these things at a wafer level in a cost-effective way that's a real alternative to doing system-level test or a package-level burn-in test. By the way, if you want package-level burn-in test, I'll sell them to you all day long with my Sonoma systems. Okay. Hope that helps. It does. What's the stability of the power over that duration? That seems like it would be a critical feature in terms of within a tight tolerance. Yeah. Some of the mini tricks and the keys are being able to actually regulate and drive power to each device on the wafer individually. Now, that doesn't seem intuitive, right? In traditional package-part burn-in systems, like those from our competitors, they have bulk power supplies that supply to each of the devices all with the same voltages. They achieve a parallelism by actually trying to share all that. That didn't work very well because each of the devices need a different voltage. Sonoma, one of the greatest things about it as a package-part burn-in system is we can individually program the power for every device that's being tested. We'll actually read an ID in the device, come back, adjust our power, and tune it for that device for an optimum burn-in. That's an amazing thing that people don't have in package-part burn-in that we do in Sonoma. We're doing the same thing at wafer level, okay? There are more tricks, and I'm just not going to do them publicly. There are other things that we've done. In fact, there are some patents you can go and find that we've done that we can implement in our wafer-level burn-in system in our wafer pack that you just can't do in a normal wafer probing environment either that allow us to be able to test these devices. It's pretty fun talking with the customers because they kind of light up as you talk about what you can do, and they're like, "Wait a minute. I've never even thought of that before." I'll give you one other hint, okay? One of the reasons everyone says this will never work at wafer-level burn-in is because these devices might, one core might take 100 amps. Maybe it takes multiple 100 amps, okay? What you do is you have a 100-amp power supply, and you run it through a probe card. The probe card needles can only do maybe half an amp or 50 milliamps, I heard somebody say the other day, okay? I have to put 100 of them in parallel, whatever the math is. Sorry. It's always tough online like this to get you to 100 amps, okay? Or 1,000 pins to get to 100 amps with this. What happens if that section of the device fails and shorts? It'll ruin your probe card. When we first engage them, they're like, "This is absolutely impossible because every wafer, I have a device that shorts in the middle of the burning, and it's going to ruin your probe card." We have features in our wafer-level burn-in systems that prevent it from doing that. We've not burnt one pin yet. We've been working on this AI with this customer at wafer-level burn-in for nine months. We've not burnt one pin, which is crazy. People are like, "I don't even understand how you do that." There are some cool things about it that are just not intuitive, that are as differentiated as anything, and we're excited about it. It's a fun market. All right. Listen, that's it for me. I'll jump back in queue. Thanks, Gayn, for the additional color. You're welcome. Okay. The next question comes from Larry Chlebina with Chlebina Capital. Please proceed. Hi, Gayn. When was the first AI processor, XP? Let's see. Was that with the auto aligner? When was that up and running at that OSAT? That's a good question. We had it up and running here first. As those that have come and visited us, they know we have these test cell labs, which we're upgrading. And we were actually shipping wafers out of our facility here. It's now up and running, the first one, and we'll have the rest of them all completed this quarter, whatever, in the next few weeks here. So. But it was running at the OSAT when? We haven't. All we've said is it's up and running now. All right. Hey, Chris, I got a quick question. What was the package part revenue in Q3? Package part in Q3. Let me look at it right now. Q3 is, in the past, we only disclose it in the end, but I would say, let me say this one. I would say more than 20%. Okay. More than 20%. It's going to be in the Q. That's all right. Hey, Gayn, is there any product launch on your flash customer that they're particularly wanting to use your systems on? I know this is an enterprise application, and I see these big SSDs coming up later this year that they have like 123 TB of data capacity on it, which if you do the math on it, they consume with a decent yield. Each one consumes like a wafer and a half of NAND just to stuff into that two and a half inch form factor SSD. Is there a product like that that's their interest in using your system to improve the yields? Because obviously, they're stacking a bunch of dies. Is that the motivation? Okay. I'm going to, boy, this is three in a row. We're answering a little bit indirectly. I just want to be a little careful of customers. We talked to multiple. There's not that many NAND customers, and we have not talked to every single one of them, okay, for some geographical obvious reasons, okay? We have talked to several of them, and there is a general theme going on with those customers and with the industry if you watch what's going on. That theme is, so a couple of things. In general, revenues are growing, okay? They were down last year and the year before, and they're growing again. Wafer capacity is not, okay? There's not a lot of NAND fabs that are coming online. The capacity may be going to higher utilization, but the bits are exploding, okay? What that means is that there's more and more density per wafer, okay? As you do that, the test methodology is either going to increase in test time or you're going to need to increase in power to address it. The other thing that's going on is there's multiple kinds of technologies out there that stacked or not stacked, that's the wrong word, layers. The NAND layers are going to hundreds of layers, which are just basically when I think of a high-rise building, there's a lobby floor, and then there's floors above. The lobby floor may have the logic on it for the interface, and the floors above are what store all of the information, okay? Now, some people might say the I/O is on the top, but don't go into that. This is on one device. They take those devices and they stack them together into a package, like you said, with an SSD, okay? One of the things that's going on in the memory itself is the die are actually getting taller, okay? To hit the right things, the footprint, the XY footprint's getting smaller, which means the die count on a wafer is getting up. The way they're getting density is they're shrinking. They're getting the footprint of that building to be smaller, and they're making it taller, okay? That's how they're getting more out of a wafer. That's causing problems with respect to parallelism and power, which is a key thing that would be driving a new requirement. The other thing that's going on is this thing around hybrid bonding. This is the first time I've talked about this on a call, okay? On the hybrid bonding, there are several people out there that are introducing products that are coming up over the next year or so that what they do is they make that lobby floor, the logic I/O on one process wafer, and then they make all the buildings or the floors that hold all the data on another wafer. Then they actually glue them together with a hybrid bond. When they do that, they can actually make the lobby floor smaller and faster because they can use a CMOS technology that will work without it that'll still because they don't have to make a memory cell out of it. They take a different technology that is good at memory cells that is lousy at lobbies or the I/O speed, and they can make those taller. Now I can make the building taller by separating the NAND cells from the lobby floor I/O, and I just have to glue them together. I say glue, fancy. There are people that do this for a living, but it's a hybrid bonding process similar to TSV bonding when you think of some of the other things that are going on in the world. If you do that. You're just using for the flash, for the NAND component of that, right? And/or the combined combination of it, etc. There's some I don't want to get into too much of it, but there's technological things that are breaking the infrastructure. Those are the opportunities to get in because it's not that someone's throwing in a new fab. Makes sense? Why would you want to go build a bunch of new equipment for that? That's the message I want to get across. That provides an opportunity for things to be disruptive enough to actually change the way your process is doing. It's not just one company. Ultimately, it would be all of them. I was just looking at one of those SSD drives and the amount of NAND that they consume for a reasonable expectation on sales of those drives. You work that number backwards, and it seems like they would need something like $70 million worth of your equipment just to process those wafers in order to improve the yield that they get as they stack all those dies on top of each other into that small package. Yeah. That was where I was going within the prepared remarks that and I'm not trying to get there's a couple of different ways of cutting this thing. If you're spending $80 billion, if you're incrementally selling $80 billion a year of NAND, and the process technology is changing to allow you to be competitive to get more bits to do whatever, what kind of spend would you be doing? It's interesting if you're saying that you're not necessarily spending it all on new capital equipment, your test budget might be bigger. Being able to spend $80 million, as you said, that's not at all out of reason. That's pretty astounding that one customer, one flash memory customer on one product could require that kind of spend in order to get the yields where they have to get them. Anyway, I want to switch. Your fine pitch wafer pack that I guess you're developing for that application, doesn't that open up the DRAM high bandwidth market for you guys? It opens, yes, in terms of being able to test the DRAM. There's other things that would need to be done in order to do that, particularly around the DFT and low pin count test modes. The interesting thing, and I've shared this, all people kind of track it over the last how many quarters. If you go back and look at what I said two years ago, I don't know whatever it was. Just any quarter prior to AI, ChatGPT, I kept saying that wafer-level burn-in will first go to NAND, and then ultimately, it will go to DRAM. In order for it to go to DRAM, the DRAM guys need to have the critical requirement. There needs to be more pain. The pain needs to be when they start stacking DRAM. When they do that, they'll have to figure out a low pin count mode and testability, or else they're going to get eaten up in yield. Now what you see is with HBM, which is still not the biggest part, but it's certainly the fastest growing part of DRAM, HBM requires this advanced packaging and stacking. Guess what? Yield's a big problem for them. You saw, was it just last month, NVIDIA came out and said publicly, "I'm now asking that all DRAM suppliers start supplying me with known good stacks of DRAM." What does that mean? Obviously, it means they're not good. I already told you 10 minutes ago that on my package part burn-in systems, when we burn in those devices, we're burning in the memories too. Why are we burning in the memories there? What a horrible place to do it. Anyhow, kind of interesting. I thought the fine pitch wafer pack, though, gets to the point where it can touch down on all those contact points on the DRAM, so it opens that up. Am I missing something there? No, no, no, not really. On these HBM memories, they might have 1,000 pins on them. They're all TSVs. They're like 10 microns. No one can touch those TSV pads, not FormFactor, not anything. They're still testability pads, but on a DRAM like that, maybe it used to have 50 pins or 60 pins or something times 3,000 die. You go through that math, that's a big probe card. And so a full wafer probe card is quite expensive, and cost-effectiveness isn't really there. If you implement a DFT mode, interestingly, like is done in the package, but anyhow, you can drop down to a JTAG I/O port or an MBUS I/O port, which is a single I/O pin. So why not do that? The NAND guys did. As that is implemented, you could see that people might drive towards a DRAM. If any of the DRAM guys are listening, I'd love to talk to you again if I'm not already talking to you about this because I think we can help. They definitely have a yield issue. Last question real quick. There's a long-term customer of yours that's ramping up on a 3D packaging facility in New Mexico. They're assembling three to five chiplets onto a subchip. I don't know. I think the throughput of that facility eventually will be at least $25 billion worth of product. At what point do you go to your customer and say, "You're already in that fab on the optical side"? At what point do you say, "Hey, what would you spend if I could improve your yields?" Some of the things you said earlier. If I can improve your overall yield 3% on those heterogeneous chips, what would they spend to achieve that going forward? I mean, every year, you only have to spend it once. Wouldn't they spend like $300 million to get that capability? I know you'd be testing all the incoming component wafers before they get singulated and put into the chiplets. Isn't that a hell of an opportunity for you guys? Okay. I have never mentioned that we have systems installed in New Mexico or all those things that you've said. I will not confirm or deny anything here. I do not want to get myself in trouble with any potential customers. Someone who is doing that would certainly be attractive to us. What we've definitely said, and what you were implying there, is that we have, what, six, seven optical customers related to silicon photonics, one in particular that has been our lead customer and a 10%er several years. Within those customers, we have worked with the largest to build this very high-power silicon photonics-based system that is amazing. We've qualified that. We shipped it for the first time, what, last year. They spent the last year qualifying. We've been doing all kinds of engineering runs and things with different types of wafer packs. We've heard that they are talking about ramping this year with these new optical devices, which the target for those are chip-to-chip or chiplet-type things when we say that out loud. I'm excited about that. I think, as you said, "Well, why not use it in every other chip along the way?" I think that's a good point. If we can do very well with what we're planning right now, maybe that opens up an opportunity with that customer, if not others. I would just, as a reminder for everybody listening on the call, our tool set primarily on the wafer level till the Intel acquisition of PackagePart was a system that was designed around these mega trends with semiconductors that are growing to a trillion dollars, where semiconductors are not more reliable year to year. They're less reliable due to line widths, the compound semiconductors like optical and silicon carbide, stacking them all together in multi-chip modules or in modules like memories that are put together for SSDs or modules that are power going into electric vehicles. Unfortunately, they're putting them in things that matter to reliability, like automotive devices or data centers or these very expensive AI processors. That opens up an opportunity to do this burn-in stress conditions on those devices before they're put into the packages. That's why the burn-in market now is so much bigger and more interesting than it has ever been in its history, at least going back to the early 1980s, because of its enabling capabilities technology-wise that otherwise you wouldn't have been able to. We are picking up customers and markets along the way. I always say, "Give it a year and we'll have another one." Larry, if you have a specific contact on someone along those lines, it would not be the first time one of my shareholders has introduced me to a customer and I got an order out of it. Thank you. That would be a big one. All right. Thanks for your time. Thank you. Thank you. Okay. Your last person in queue is Charles Tao, private investor. Please proceed. Hi. Good morning. Good afternoon. Thanks for taking my question. I think my first question has been asked by Larry. My second question is, again, if everything is on track, when do you expect to receive mass production orders from the flash memory company you are currently working with? Yeah. It's a good question. What we've said, right or wrong, is that we're trying to be relatively visible. It's always a little dangerous with all your potential competitors listening in, is that this year we spent the year working on some technological steps to prove the proof of concept of our low-cost test cell that is really around this wafer pack carrier that allows everything else to be lower cost and allows higher power, higher density. With that, our hope is, upon successful completion of that, which we were targeting to try and be around this next quarter or so, we then want to work with the customer around the next step, which would be in co-development of a test system that would go into that machine. We think that's going to take about a year or so. Maybe it could take longer, but there's reason to believe maybe a year. I wouldn't expect volume orders for that until the following year. We're a year out or so. But you know what? If you told me I was taking volume orders and shipping for revenue in our fiscal 2027, which begins in June of 2026, I would tell you that's awesome. Okay. Yeah. What size? How big the site can you imagine? How big is the site? Size? The size? Yeah. The size of the market? Yeah. I mean, this is where what we think is if you were to look at, and I don't want to pick on any customer, okay? But the market just this year is $80 billion. I think it's growing at maybe 10%-20% revenue. Bits are growing 40%, something like that. Two years out from now, I mean, okay, maybe it's $100 billion, something like that, how much that is. You divide it by what? There's six customers, five customers that matter. They are not all even, but each one has 20%, maybe a little less, okay? That spend by them is substantial. The cost savings advantage to be able to do that would be substantial. In order for us to actually help them with yield, there is a considerable market. This is embedded in the number that I said during my prepared remarks, that the total available market is a combination of $500 million in test and $500 million in consumables. The flash memory could be certainly 10%, if not more, of that overall market. $100 million-$150 million, just wafer-level burn-in for flash memory in that timeframe, minimum. Okay. Thank you. You're welcome. If there are no further questions in the queue, I'd like to turn the floor back to management for any closing remarks. All right. I appreciate everybody, as always, for jumping on here. I just wanted to, before closing the call, just one personnel-related thing I hadn't gotten to. I'm just happy to announce the addition of a new member to the team, Didier Wimmers, to our organization as our EVP of Engineering. He's replacing Avi, who, as we previously announced, passed away unexpectedly last year. Didier is an incredible addition to Aehr. He brings decades of direct experiences leading engineering teams in semi-test. He's pretty well known. I joked around and said he's famous in the ATE space. He headed up all of Schlumberger ATE for many years, also managed the engineering team at FormFactor, who's basically one of the largest semiconductor test probe card companies in the world. I worked with FormFactor for many years in my memory experience before, and that's where I had met Didier in the past. So I've known him for a long time, maybe 20 years myself. He's a great leader, extensive knowledge in ATE, wafer probing, great experience. He's a great manager and also a nerdy guy, which I say very in a warm way. He's a great member, team member. I'm excited to have him on because of his experience in ATE, system-level testing, and even burn-in systems before joining Aehr. We welcome him on board and excited to have him. As always, we appreciate everybody joining in. If you happen to be anywhere near the Bay Area and are interested, we can try and set up something. Our facility here, we're getting right down to the final of it. We're about a month away from it being pretty well completed. We've done a little bit of just a remodel in general for cubes and facility areas for the employees, which they really love. We did a major remodel in the manufacturing and the cleanroom labs, which allow us to increase both manufacturing prototype engineering capacity, but particularly manufacturing capacity of our systems, our new package part systems from Sonoma, that those systems will be coming over here over the next couple of months, and also our wafer packs and our BIM consumables from the package part side. All that will be consolidated here Q1-ish, I don't know, this summer, okay? If you come by then, we'll probably be finally happy with everything kind of put together, and all the lights are up and everything too. I thank you, everyone, for your encouragement. I've gotten a lot of calls. I've hung in there. A lot of people very excited about the stuff that we're working on. We're all kind of enduring through all these tariff things, but this too, my favorite saying, "This too shall pass." Thank you all, and we'll talk to you next quarter. This concludes today's conference, and you may disconnect your lines at this time. Thank you for your participation.