Hello, and welcome to today's event. I'm Mike Sullivan, Head of Investor Relations at Applied Materials. We're launching two new products today during the SPIE Lithography and Patterning conference. Before we begin, I'd like to give you some context on how today's product introductions fit within the industry. What I'm showing you here are three ways to segment the wafer fab equipment market. You're probably familiar with the segmentation on the left, which is by equipment type. You can see the Applied Materials segments and share in blue. In the middle, you can see the equipment markets by device type, DRAM and NAND, along with foundry logic, both leading-edge and ICAPS. On the right is the way engineers often segment the market, which is by application. The four major applications are patterning, which is used to define the features on each layer of the chip, along with transistor formation, interconnect formation, and advanced packaging. Patterning includes lithography and track tools, these tools primarily transfer patterns from masks to photoresists. Patterning depends on many other tools as well, for example, to deposit patterning films, measure pattern accuracy, and etch patterns into patterning films, as well as into wafers. On the right side of this chart, you can see that Applied offers eight kinds of tools for these other patterning applications, including a brand-new kind of tool that we'll introduce to you in a moment. Patterning has been a big focus for our company since 2013, and we anticipated at that time that our patterning markets would grow faster than WFE overall. Our opportunity has grown from around one and a half billion dollars in 2013 to over $7 billion in 2021, and our share of this opportunity has grown from less than 10% to nearly 30% over this period. Today, we're gonna introduce two new products, the newest member of our EUV metrology family, and this brand-new technology called pattern shaping. Here is today's agenda. First, Steve Sherman will introduce you to the new technology called pattern shaping, that can replace EUV steps. Keith Wells will introduce you to a new metrology system that will help to enable High-NA EUV. Finally, we'll help answer your questions. A quick housekeeping notice, we've already posted all of the slides and the supporting materials from today's presentation on the IR page of our website at appliedmaterials.com. Now I'd like to hand the meeting over to Steve Sherman. Steve? Thanks, Mike. Before we get into pattern shaping, I'd like to introduce a few simple patterning concepts that'll help and make it easier to understand what we talk about later. On the upper left is a simple line space pattern, sometimes called a grading pattern. Many of today's critical patterning layers start with a simple line space pattern. Next is a cut mask. These are holes or trenches that are used to segment the lines in the line space pattern. Last, we have vias. These are holes that are later filled with metal and are used in interconnect wiring. They connect one metal layer to the next. On the left graph, we illustrate what we call the lithography gap. This is a gap between lithography resolution, which is the green line, and the minimum critical dimensions that chipmakers would like to pattern, which is the blue line. Over many decades now, different materials engineering techniques have been used to close the lithography gap. Today, we're gonna talk about one specific critical dimension called tip-to-tip spacing. In the lower right is a cartoon with a line space pattern. The gray lines can be thought of as trenches in the blue material. Also, you'll see an x and a y-axis next to the image. In order to shrink die size, you have to reduce dimensions or shrink dimensions in both the x dimension and the y direction. In the y direction, this is done by shrinking pitch. In the x direction, this is done by shrinking tip-to-tip spacing, which is the space between opposing line ends. In today's EUV lithography equipment, many optical tricks are used to improve resolution in one direction only. In this case, you could say the y direction, which is used to reduce pitch and pattern the tightest pitch possible. Most of these tricks that are played to improve resolution in one direction end up sacrificing resolution in the opposite direction. The tighter pitch that you try to pattern, the your ability to pattern tight tip-to-tip decreases. I put some numbers to that in the table above. These are for a line space pattern of about 32 nm pitch. That is a 16 nm line and a 16 nm space. This is about the practical limit of what can be patterned today with a single EUV pass. For a 32 nm pitch line space, the tightest tip-to-tip that can be patterned is in the range of about 25 nm-30 nm. If chipmakers want to pattern a tighter tip-to-tip spacing of about 15 nm or 20 nm, EUV double patterning is required. We'll talk about a couple of different examples of EUV double patterning in the next couple of slides. On the left is a two-scale image of interconnect wiring. The metal lines route signals and power within each layer of a chip. The lower metal layers are critical layers where chipmakers are pushing the resolution of EUV lithography. This is where we want to pattern dimensions that are beyond the resolution that can be done in a single EUV mask. On the right, we show one example of EUV double patterning. We start with one EUV mask, which is a simple line space pattern, as we described before. Here, the gray lines again, are the spaces and can also be thought of as trenches. We go to a second EUV pass or a second EUV mask, to print what we call a block mask, where we add material and effectively segment the trenches and define the tip-to-tip spacing of those trenches. Here, we pattern, we have the full pattern, and we've created a tip-to-tip spacing that is not possible with a single EUV mask, because it's beyond the resolution of one EUV mask. In this slide, we show a similar example for vias. Again, the lower via layers are where we're critical layers, where we're trying to print dimensions that are beyond the resolution of a single EUV mask. This is where multi-patterning is used. On the right, we show a different example of EUV double patterning. Here, we start with the first EUV mask, where we print only half of the pattern. Only about half of the vias are patterned here. In this way, we can get a tip-to-tip spacing between the vias that is well within the lithography, the resolution limits of a single EUV mask. We follow with a second EUV mask, where we print the second half of the pattern. In this way, we can achieve a tip-to-tip spacing that's beyond the resolution of a single EUV mask. In both of those examples, we went through the EUV lithography twice. Here we show a simplified process flow of EUV double patterning. You can see the two lithography steps and also all the associated steps, including patterning layer depositions, etches, cleans, and metrology. As we've explained, this technique is effective at getting all the critical dimensions that we require. However, there are undesired consequences, and those are shown in the boxes at the bottom. First, is alignment errors. Because we have two masks, the second mask must be aligned precisely to the first. If it's not, this can cause litho rework, where the photolithography is measured for alignment, and can be the photoresist can be cleaned off, re-spun, and get a second try through patterning. Any alignment errors that remain as the wafer goes downstream, will result in chip performance and power issues, and if the alignment is very bad, yield loss. The middle box, we describe the energy and materials used for each EUV litho LE loop. LE stands for litho etch. We estimate about 25 kilowatt hours per wafer, about 0.5 kilograms of CO2 equivalent emissions per wafer, and about 15 liters of water per wafer, per LE loop. On the right box, we show the cost. We estimate about $350 million of capital cost per 100,000 wafer starts per month, and about $70 per wafer manufacturing or OpEx costs per wafer, per EUV loop. Now we'll talk about pattern shaping. On the left is the same EUV double patterning we talked about earlier, with a line space pattern and a block mask. On the right is today's news or pattern shaping. Here, we pattern with one EUV pass only, where we pattern the line space pattern as before, but including the tip-to-tip spacing. The tip-to-tip spacing is patterned wider than desired, but within the resolution limit of a single EUV mask. We move to the pattern shaping tool, where we elongate the trenches, thus shrinking the tip-to-tip space to the desired spacing. In this way, we're delivering all the dimensions, the pitch and the tip-to-tip spacing that we desire, but with only one trip through the EUV tool. Here is the similar for the via example. On the left is the same double patterning technique we talked about earlier, with a first EUV pass with half the vias pattern, and then the second in the second pattern, EUV LE. On the right is the pattern shaping example. Here, we use one EUV pass, where all the vias are patterned in one mask, but with a different shape, such that the tip-to-tip spacing between the vias is within the resolution of one EUV mask. We move again to the pattern shaping tool, where the vias are elongated such that the tip-to-tip spacing is reduced. In this way, again, we deliver all the dimensions of EUV double patterning, but with only one pass through an EUV tool. This is our first pattern shaping product. It's called the Centura Sculpta Patterning System. It's a breakthrough innovation for the patterning engineer's toolkit. It's a brand-new capability in the fab. It enhances EUV patterns to optimize chip area and cost without EUV double patterning, reduces patterning complexity, reduces the environmental impact of advanced chip making by saving energy, materials, and water, reduces capital and operating costs, it's extendable to high-NA EUV patterning. This has been in development for over 6 years in collaboration with advanced logic foundry customers, recently, we've been chosen production tool of record for multiple layers in leading-edge logic. Here, we'll share a 3-minute video on pattern shaping technology. The first half of it is somewhat repetitive to what we've talked about before, in the second half, we'll describe how the tool works. Applied Materials' pattern shaping technology is a breakthrough innovation for the patterning engineer's toolkit. In this animation, we will show you how engineers can replace EUV double patterning steps with the Centura Sculpta Patterning System to reduce the cost, complexity, and environmental impact of leading-edge chip making. Advanced chip makers use EUV lithography to create more dense patterns than immersion lithography permits. Even EUV has limits to how close together features, such as these interconnect vias, can be placed using a single EUV mask. Here, we depict the tightest spacing possible using a single EUV pass. The designer may want to reduce this spacing by around one half to optimize die area and cost. Conventionally, such tight spacing requires EUV double patterning. Here's how it works. First, patterning films are deposited on the wafer. An EUV lithography step exposes half of the pattern in the photoresist. Next, a number of materials removal and process control steps are used to replicate the photoresist pattern in the patterning layers. Finally, all of these steps are repeated to transfer the second half of the pattern to the patterning layers. It is critical to properly align the second part of the pattern with the first. Applied's pattern shaping technology allows this dense pattern to be fabricated with only one EUV lithography step. This eliminates double patterning alignment errors and saves all of the time, energy, materials, water, and cost associated with the second patterning sequence. Here's how it works. First, one EUV step is used to expose round vias within the spacing resolution limit of EUV. The wafer is moved to the Applied Centura Sculpta system for pattern shaping. The Sculpta system uses a unique angled reactive ribbon beam to sculpt the patterning materials stack. As the sidewalls are exposed to the beam, chemically reactive species and radicals precisely remove patterning material to enhance the shapes. The wafer can be rotated in any direction to create desired shapes without any additional lithography. In this via shaping example, the vias have been reshaped from round to elliptical. The tip-to-tip spacing has been reduced, and the risk of EUV double patterning alignment errors has been eliminated. This animation described the first of many potential applications made possible by the Applied Centura Sculpta system. Applied's pattern shaping technology is a breakthrough innovation, adding new capabilities to the patterning engineer's toolkit. Sculpta reduces patterning cost and complexity and lessens the environmental impact of advanced chip making. Here we show the same simplified process flow for EUV double patterning that we showed earlier on the top. On the bottom is the simplified process flow for pattern shaping. You can see the same one EUV loop, but then the second EUV loop is replaced with pattern shaping. Here we quantify some of the savings using pattern shaping. First, of course, because there's only one EUV loop, there are no alignment errors. We've eliminated one opportunity for alignment errors in the overall chip-making process flow. In the middle, we show the energy and material savings we estimate, about 15 kWh per wafer saved, about 0.35 kg of CO2 equivalent emissions per wafer saved, and all of the 15 L of water per wafer saved. On the right, we show the cost savings. We estimate about $250 million of capital cost per 100K wafer starts per month, and about $50 per wafer of manufacturing costs saved. In our press release, we have a few quotes that I have here. The first one is from Intel, talking about what they see as the main value of pattern shaping. The second is from Samsung, also describing what they think is good about pattern shaping. The third is from an industry analyst, Dan Hutcheson, talking about the importance of pattern shaping. I'll hand it over to Keith Wells, who's gonna talk about a new eBeam metrology tool. Thank you, Steve. Back in December, we talked about the eBeam market, and in particular, we focused on defect control, and we introduced two new products: the SEMVision G10 and the PrimeVision 10. Today, we're going to talk about the patterning control segment, and here, we're going to introduce a new tool called VeritySEM 10, which is a critical dimension metrology tool. What is a CD-SEM? It's often called the ruler of the fab, and what it's used for is to make extremely precise and accurate measurements of the line and spaces that our customers are trying to print, as well as the pitch. It's even gone beyond that. It actually measures what's called line edge roughness or line width roughness on the device. Our customers use this to optimize their EUV steps in the fab today, and have been highly dependent on this technology for over 30 years in order to monitor their process and get high yield. Let's look at how it's applied in the fab. It's used in two main process steps. One is the lithography loop, where after the lithography tool exposes the resist, the CD-SEM is used to make sure that both the line widths and the pitches are patterned correctly. Here, the customer, if they do find errors, are able to rework the wafers. They're able to strip off the resist and then go back through that process. The CD-SEM is an important quality monitor in the lithography loop and really can end up saving our customers millions of dollars. If the lithography is patterned correctly, then the wafer is transferred to an etch step. In the etch step, what we do is we look at the critical dimensions after the wafer's been etched. Here, the customer will make a decision whether or not to proceed forward with the wafer. If the etch step was unsuccessful, unfortunately, the customer, at this point, has to scrap the wafer. If the etch step was successful, the information from the CD-SEM will be transferred back to the litho cell in order to do co-optimization between the lithography module and also the etch module. You can see the precision that customers want from this type of tool, actually demanding precision and accuracies in the sub-one nanometer range in order to properly monitor the process. Let's give an example of how this type of tool has been used in the litho module. If you go back a few years ago, when we were primarily using deep UV patterning techniques, the pitches might have been on the order of, say, 70 nm, the process window, ±1 nm, and the SEM precision had to be about one-tenth of the process window or 0.1 nm. In general, we were using landing energies that generated resolutions of about 1.4 nm to 1.6 nm. Taking that same type of technology and using it in EUV and High-NA EUV is going to be problematic. Here you can see the actual pitch is about half in the 30 nm range for most EUV steps. The process window has become tighter, and therefore, the SEM precision requirement has also become tighter. If we go and we look at High-NA EUV, it's only gonna get more challenging. Here, we're seeing the pitches in the 20 nm range, the process window at 0.5 nm, and therefore, the precision at 0.05 nm. This represents a challenge for us in order to try to meet these type of specifications, especially in the High-NA EUV steps. How do we build a tool that can meet those challenges? Well, typically, what you do with a e-beam tool is you actually increase what's called the landing energy or the energy of the electrons, and the more energetic electrons you use, the higher resolution you'll have in the system. That works for most steps, but unfortunately, when you look at EUV resists, they're actually quite delicate, and the interaction with high-energy electrons can actually damage or shrink the resists. This is a common phenomenon in the industry. You've got to pick a balance between using as much landing energy or as high as landing energies as you can to increase the resolution, but not damage the resist. This is an example of kind of the trade-offs that you have to make. Here, we're trying to figure out what landing energies we can use in a new CD-SEM in order to meet the resolution requirements. The concept is really that you have an operating range or a working landing energy range that you have to determine. You have to engineer the tool such that it has acceptable shrinkage of the resist when making the measurement, but also has the required resolution to meet the demands of High-NA EUV. Let's go back to our example here, and what we saw back in the deep UV patterning area, that working landing energy range was fairly wide, and the SEMs used back at that time were able to meet the requirements of the deep UV steps. If you take that same technology and you try to apply it to EUV. It works, but then the operating range or the landing energy ranges you can use have shrunk considerably. The customer has far fewer options in around the operating points of how they can use the CD-SEM in the fab. What we're trying to do with the VeritySEM 10 is re-engineer a tool that will expand the landing energy working ranges for the high-NA EUV. Today, we've introduced this product for EUV, but we've also future-proofed it such that it can be applicable to high-NA EUV with these wider landing energy ranges. The VeritySEM 10, to recap, really has lower landing energy in order not to damage the delicate EUV resists. What we had to also do was to redesign the column in order to get the resolution to the requirements of EUV patterning. We've done both in this tool, both given our customers lower landing energy operating points, as well as increasing the overall resolution of the tool. This leads to minimum resist shrinkage, and we've also made the tool faster, so it's going to be also 30% more productive versus earlier versions of the CD metrology tool. If we go back to our example, and we look at what this tool will be able to do as we go forward and adopt more EUV patterning steps, then finally adopt High-NA EUV patterning steps, here, we're able to almost double the resolution, going down to sub-1 nm resolution, and deliver an overall range of 0.8 nm to 1.2 nm resolution, and we're able to do that at landing energies that are far below 300 volts. That will give us the resolution needed to monitor the High-NA EUV steps. We did a lot of engineering of this tool to address, obviously, the litho module, but what else did we do in the tool? There's 2 other applications that we targeted for this tool. One is gate-all-around applications, where we've added in backscattered electrons to enhance our ability to give us contrast on these critical gate-all-around steps. We've also enhanced the product for 3D NAND in order to give customers the capabilities they need to properly monitor their 3D NAND steps. Let's take a look at a few examples here. But before I do that, I want to talk a little bit about what backscattered electrons are. Again, back in our webinar in December, we introduced this slide, and traditionally, what a CD-SEM does is it collects secondary electrons. Secondary electrons are generated at the surface of the material that's being monitored, they're very sensitive to things like contact openings. That's how traditionally CD-SEMs have been designed, to mainly collect the secondary electrons. You can gather more information if you use backscattered electrons. Backscattered electrons can penetrate down deep into Vias, they can give you information about material in the bottom of the Vias or the bottom of trenches. Getting that information and back up and detecting it gives you much sharper contrast between the holes at the top and the structures at the bottom of the wafer, then allows you to make more precise CD measurements. That's we've applied this type of concept to a gate-all-around structure. Here, what you're seeing in the gate-all-around structure is an example of epitaxial fill down in the trenches. Now, because the epitaxy is clearly a different material than the gate on top, we're able to use backscattered electrons to generate contrast of the epitaxial material, and that tells us whether the fill of the epi has been done correctly. We can obviously check for ideal fill, overfill, underfill, things as partial fill, and voiding down in the epi layer. What we're giving our customers is not only the ability to measure CD-SEMs in this step, but we're also giving them the ability to monitor another process when they use the VeritySEM 10 and apply it to this type of application. Here's an example of how the VeritySEM is helping our customers in 3D NAND. Here, a critical part of the 3D NAND patterning is what's called the staircase step. Here, there are very complex interconnects, and they're patterned over a very large area at the semiconductor device level, over 60 micron in area. The overall aspect ratio in Z dimension can be over 10 microns. What our customers want to be able to do is to use a VeritySEM 10 to go in, and in a single imaging step, image that 60-micron field of view in X and Y, as well as get information across the whole depth of field of the 10 micron step. We've engineered the tool with a wide field of view, as well as a very generous depth of focus, in order to allow our customers to do this type of monitoring step. And therefore, we've made the VeritySEM 10 much more flexible than just a CD-SEM. Today, we've introduced this product to the market. We have over 30 systems shipped. We have tools of record in development for gate-all-around at leading-edge foundry and logic customers. We have placed multiple tools at customers doing DRAM for both production steps and the EUV modules in those production steps. Finally, we also have both development tool of a record and production tool of record wins at 3D NAND customers. Here's an example of kind of the history of the CD-SEM within the PDC business unit. If you go back 10 years ago in 2013, we had barely 14% of the market back then, and you can see for logic and foundry, we had only 5% of the market. Starting with the VeritySEM 5i, approximately 6 years ago, we built a tool where our customers found it very productive and basically started applying it more and more to critical foundry and logic steps. Our market share increased to roughly 25% in that area. With the introduction of the SEM 6i and 7i, we further gained market share in 2021, approaching 40% of the overall market in foundry logic and 34% of the entire semi market. With the introduction of VeritySEM 10, today, we believe we can extend our market share gains in this segment. Today, or during this week, SPIE is taking place, and we have four customers that are presenting papers around how they're using the VeritySEM 10 in their applications and their fabs. If you have a chance this week, check out these talks. With that, I'm gonna turn it back over to Mike for question and answers. Great. Thank you, Keith, and we hope you really enjoyed learning about Sculpta and the new VeritySEM 10, from Steve and Keith. Now it's time for the Q&A portion of the meeting. There's two ways to ask a question today. One, you can use the raised hand feature in your Zoom window, and I'll call your name out. It will ask you to unmute your line. You'll be invited to do that, and then we'll be able to hear you and take your questions. By the way, you know, we have more time today, hopefully, than on the earnings call, so if you have more than one question, feel free to go ahead and ask it today. Secondly, if you prefer, you can also type your question into the Zoom window on your screen, and I'll just read that out for you. What we'll do now is we'll pause, and we'll see if we have anybody who would like to take a question. Okay, we believe we do have a question in the audio queue, and that will come from Krish Sankar with Cowen. Krish, can you unmute your line for us? Hey, Mike, can you hear me? Yes, we can. How are you? I'm good. Thank you very much for taking my question. I had a few of them. First one, just to clarify, Steve, when I saw the animation for the Sculpta, it said it was a ribbon beam. Is this not a etch or adapted technology? Is it more like laser or something like that? I had a couple of follow-ups. Yeah, it's a good question. It's a plasma ribbon beam. It's similar to etch in that it's material removal. That's probably where the analogy ends. You know, etch is mainly used to transfer a pattern, an existing pattern in photoresist and transfer it into the wafer, whereas here, we're shaping the mask itself. Got it. Is there a way you can help us quantify today, how many double patterning steps are there in EUV, in the N5, N3, N2 nodes, and with pattern shaping, what would that be for each of those three nodes? Yeah, I won't get into specifics about the nodes. It varies widely between customers. Everyone has different patterning schemes. Certainly, through those nodes, the number of multi-patterning layers goes up, node by node, everywhere. I would say, you know, you said 5 nm, 4 nm, 3 nm. By the time you get to 3 nm, and beyond 3 nm, and 2 nm, you know, it's a few. It's more than a few, I'll say, more than a few in the advanced nodes. Got it. Got it. Then maybe a final question, and I'll get back into the queue. How should we think about this? For example, like, you know, pick a node 5 nm or 3 nm. Like, let's say, you know, we heard, like, TSMC has publicly said a 3 nm, they have, like, 24 EUV layers. At 3 E, it's more like 18 or 19, so you've seen a reduction number of EUV layers. Is there a way to quantify how much EUV layer reduction you would see or litho tool reduction you would see as you use AMAT's pattern shaping? Yeah, that really depends on how aggressively to the customers adopt pattern shaping. Yeah, hard to answer. I know. Maybe one last thing, I can get back to the queue, Mike. Sorry about that. Historically, you folks have had some market share in patterning, you know, through your depth and sorry, probably on the edge products. Now with pattern shaping, is it cannibalizing some of that opportunity? Thank you. Yeah, it's a good question, too. I would say, and I'll let Mike jump in, too, but I'd say it's net positive for Applied Materials, the more pattern shaping that gets adopted. Most of the cost savings is in the lithography. Really, the main goal here is just to reduce cost of chip making overall, the overall cost. You know, in the end, we think this really helps everyone. It helps our customers, and then that should make it possible for them to continue to invest across the board. Yeah. Thank you very much. Okay, thanks, Krish. Next in the audio queue, we have a question from CJ Muse, we believe, from Evercore ISI. CJ, can you hear us? Yeah. Can you hear me now? Yes. Hi. Perfect. Good morning, thank you for hosting the call. I guess just to follow up on the last answer, you talked about the main goal being reducing costs. Yet, you know, the number you put up, $250 million on 100,000 wafers, is really, you know, about 1%. That doesn't seem like very much. I would think that there would be other benefits that would really drive adoption here. Can you kinda speak to how you came up with this cost savings number? You know, is it truly cost that will determine kind of adoption, or are there other factors in your view? Certainly there are other factors. I think cost is the main factor, though. A couple notes: the estimates we gave there are per layer adopted, you know, per critical layer that's adopted. For each time you adopt a layer or use pattern shaping in a layer, you would save those, and it scales with the number of layers that you adopt. The cost can add up, and it is significant. Also, there are many other factors we mentioned. You know, the complexity is probably number one. The complexity of multi-patterning is very difficult for our customers, and it leads to longer development time. Eventually, you know, those alignment errors can lead to performance and power issues. Yeah. I think all of those are important. You know, hypothetically, let's say there's a customer in a future node who had eight steps that were EUV double patterning steps, and they chose to deploy our technology for just four of those steps. They'd be saving $1 billion for a 100,000 wafer start fab. It can add up to some very large numbers, and, you know, what customers do will, of course, be their choice. But the savings can be very large, and that's the capital savings. We also talked about the per wafer savings, so if you care about your, you know, gross margin per wafer, this can really help. The other, you know, trend that we're seeing is that a lot of people have become interested in the energy consumption, the electricity needed to run a fab, especially a fab that uses EUV technology. Tons of electricity, the materials, and the carbon equivalent of those materials, water, people care about. Fabs are being built in the desert, this tool is able to save on all of those areas as well, not to mention the technical and the economic aspects. I hope that makes sense. A follow-up question is really around customer adoption. You know, N3, N2, you know, design tool of record... pretty much well-formed, right? I would think that, this is, very much incorporated into customers' kind of roadmaps and planned width of layers. Can you speak to kind of where, what this kind of status is in terms of the big three and maybe, you know, size, you know, what this opportunity could look like for you guys in the coming, you know, handful of years? Yeah, we'll see how it goes, but I would say we're engaged at various levels with all the leading logic foundry customers. We've just started, you know, at the very early stages. We've got our first adoption and shipping our first revenue systems. You know, we'll just have to see how the other customers, how all the customers, adopt. Yeah. No, it's a great point, and, you know, a lot of times what happens, CJ, is, you know, we'll work for years, especially on a technology like this. This is something that only comes along, you know, once every great while. It's a brand-new kind of tool. It's something that didn't exist on the menu at all. The idea was there. It took, you know, Steve talked about six years working with customers, actually working with them, introducing them to the idea, and getting comfortable with the idea, and we've kind of kept this in our back pocket until we began to get commercial, you know, orders, and now that we're shipping for revenue into production. We have enough confidence that we were willing to go ahead and make public what we've been talking about. We'll have to see at this point, you know, what customers do, you know, how broadly, at what pace. The other thing that's interesting is, because it's a new capability, it'll take months and years for people to discover what they can do with it, and we'll probably be surprised by some of the applications that people come up with. Thank you. Thank you. Okay, I'd like to take the next question from the audio line, and it's Vivek Arya from Bank of America. Okay, Mike, can you hear me? Yes, thank you. Thanks very much. Thanks for the event. My question is actually related to the prior two questions as to: When does this start impacting Applied Materials? You know, is this a growth opportunity for you in the next one or two years? Does it become more impactful when N2 rolls out a lot more, right? You mentioned that you're just getting started. It sounds like a very exciting technology, but, you know, how much time would it take for the customers to pull this in into their process? Is this something that we should, you know, let's say, pencil into our models for 2025 or 2026, or is it something that is more kind of medium-term than that? Yeah, I would say, Again, I'll let Mike jump in, first revenue is now. It's relatively small, you know, we expect this to grow over the years, I would say medium term years. You know, the next two to three to four years, we should see this start to ramp. You know, one way I could add to what Steve said: you know, we have had a longer-term financial model, and, you know, with revenue expansion expectations through 2024, there is a little bit that was already in that model for this product, but of course, most of the growth of this product would be beyond that. Maybe the other thing, maybe I could ask it this way, Steve, you know, would you be disappointed if you didn't generate lifetime revenue that was well over $1 billion? Yeah, I would be disappointed. Yeah. Okay. A good way to put it. Yeah, we vision this to be a billion-dollar product. I think it's safe to say it'll be hundreds of millions of dollars per year in that timeframe. Yeah. Earlier, you know, at the beginning, I walked you through our patterning, served available market opportunity and our share, and that, you know, gave you something like a ballpark number of around $2 billion in revenue in 2021. This product alone has the opportunity to greatly accelerate our penetration into this part of the market. Got it. For my follow-up, Mike, you know, you guys said something interesting, that let's say a customer would adopt this out of, you know, X out of, you know, eight layers. What would make a customer not adopt this? Right. If the value proposition is so clear, what could be the other factors that would cause them to not adopt this solution? Yeah, it's a good question. I think, you know, patterning, there's just dozens of different patterning schemes that customers develop themselves and choose between different layers, and some of them are very, I'll say, straightforward to implement pattern shaping for, and others are not as straightforward and will take a longer time to engineer in. That's, you know, that's one reason. The final one, this is probably a dumb question, but, is this beneficial outside of the EUV environment also, so if somebody's using DUV or other litho? Does this only have benefit in EUV? Yeah, it's a great question. Theoretically, it can benefit any type of lithography. It could be used for any, you know, any node, any, any type of patterning schemes or any type of patterns. It's just that an EUV is where the value is the highest, so that's where we're gonna see, I think, for the foreseeable future, that's where we'll see all of the adoption. But, you know, theoretically, there's no reason it can't be adopted anywhere. There's no China restriction of any kind, right, on this? You know, for the same reason, you know, currently, as far as we can see, we're only targeting the. Leading edge ... customers that are, that are using multi-EUV patterning. Great. Thanks very much, gentlemen. Appreciate it. Yeah, thanks, Vivek. The next question is going to come from Toshiya Hari with Goldman Sachs. Toshiya, could you unmute your line? Hi, can you hear me? Yes, we can. Hi. Okay, hi. Great. Thanks so much for hosting this. Maybe bring Keith into the conversation here. A question on VeritySEM 10, if I may. Based on one of the slides that you showed, you guys have done really good, a good job in gaining market share in CD-SEM, broadly over the past, you know, seven, eight years. You talked about the breadth of customer interest in the VeritySEM 10. I guess, can you speak to the differentiation of this tool vis-a-vis your nearest competitor in Asia? Do they have anything sort of close to what you're introducing today from a technology and cost performance perspective? A great question. Thank you. The VeritySEM 10, I think the differentiation that we see is the ability to go to these very low landing energies. In the slides, you know, we said below 300 eV, the tool really operates quite a bit further below that. What we're seeing is we're able to do very precise and accurate measurements with very limited resist shrinkage. We think that, from what we can tell, we think we're ahead of our competition on the order of one to two years with this type of technology. Every place that we've gone and introduced the product, you saw there were over 30 systems out there. We tend to validate the fact that this is a unique capability for the tool. Understood. Thank you for that. Then one for Steve on the pattern shaping side of the portfolio. Maybe ask the market opportunity question in a different way. With the customer where you've secured the PTOR, can you speak to, you know, how many of these tools that they would need to buy from you guys for every, you know, 100,000 wafer starts per month, assuming, you know, one layer or two or three layers, what have you? Yeah, I probably shouldn't answer that question. It's. There's a few things we don't like to talk about. One is, you know, the throughput of our tools, and, yeah, I don't think we can answer that. Yeah. To your prior comment and Mike's comment, a couple hundred million dollars in a couple of years, I think you said, is sort of how we should think about the opportunity at a high level? Yeah, I think. Yeah. A few hundred million dollars in the next few, you know, per year, for the next few years is roughly right. Okay. Reasonable goal. Thank you so much. Yeah. Okay. Okay. Thank you. Great. You know, your question, Toshiya, was really a good one. You know, just as a matter of principle, we don't disclose average selling prices, and I think if we were to give units per, you know, you'd pretty soon be able to back into it. I think what you probably can tell is that there's a great deal of value that's being delivered when a customer chooses to deploy this. You would have to imagine that, you know, we're going to do our best to share in that value as well. Our next question is gonna come from the line of Harlan Sur with JP Morgan. Harlan, we're gonna invite you to unmute. Can you guys hear me? Hi, Harlan. Yep. Hi. Yeah, good morning. Thanks for hosting this event. On the Sculpta patterning product, good to see the team unveil and commercialize this product and your directional etching technology. You guys did give us a sneak peek back in April, thanks for that. You articulated manufacturing cost savings, which I assume bakes in faster process module throughput advantages of your single-pass solution. Can you guys just give us a rough sense on the throughput differences, let’s say, at Via 0 formation in a foundry logic process, your Sculpta-based approach versus the EUV double patterning approach? Yeah, throughput might not be the right question to ask. Maybe cycle time- Cycle time. Yeah, cycle time. Sorry. Yeah, cycle time is significant. It's a good question. Is more something to ask the customers. You know, it's the customer's process flow that's gonna determine that. Yeah, it can vary widely, but to save a whole EUV loop, I hesitate to answer. It's significant. It takes a lot of time to get a lot of wafers through that loop, but yeah, I think it's too hard to answer. It really depends on the customer and their scheme. Okay. Back in April, there was another innovative use case, which was more kind of manufacturability focused, which was hard mask defect removal. Can you guys just give us an update on potential commercialization of such a solution? Yeah, absolutely. I would say all of the customers we work with, explore all the different kinds of applications we've, you know, we've worked together on. I'd say mask elimination is always number one. Yeah ... it's the most compelling, and it's the one that we thought would get adopted first, and is in fact the one that was adopted first. I think the defect reduction, stochastic bridge defect reduction. Yes ... is right behind it. All the customers are exploring it or working on it. Yeah, thanks for remembering that, Harlan. I believe that's in the New Ways to Shrink masterclass. Yeah that we did. That's right. Yeah. Those slides are still out there. If somebody, you know, is not familiar with this and doesn't remember it the way you do, we did depict what those bridge defects would look like and how we could clean those up prior to etch. Yep. We'll stay tuned. Just one last question: in process control, you know, the team has, as you mentioned, driven strong market share momentum in eBeam. You guys do a really great job of leveraging your foundational technologies across all of your platforms. Again, you guys had a master class actually back in December, right, on your cold field emission technology. A lot of advantages of CFE, right? Narrow beam, higher resolution, which actually seems to be the key features integrated into the VeritySEM 10 platform. Is VeritySEM 10 based on this differentiated CFE technology? It's a really good question, and the answer very simply is no. It's actually based upon TFE technology. We were able to get the performance of the resolution and the low landing energy without using the CFE technology. The reason we made that decision is because this segment is somewhat cost sensitive, and there is a strong competition in this segment. We decided that to have a tool at the right price point, it would be better to try to engineer it to use the TFE technology. The CFE technology would be better, you're correct. in that assumption. It does drive a fairly significant cost into the engineering of the product. I wouldn't rule out us eventually taking the CFE technology to the Verity platform and using it in CD applications, but today, we didn't need to do that in order to meet the high EUV NA requirements. We didn't build the cost into the tool. Perfect. Thank you very much. Yep. Okay, thank you very much, Harlan. Our next question is going to come from the line of Pierre Ferragu, who's with New Street Research. Pierre, we're going to invite you to unmute your line. Hey, can you hear me well? Hi, Pierre. Thanks. Steve, I was wondering, you know, on this question, of, you know, how far can, like, the pattern shaping technology be adopted? Like, the limitation I can, like, understand from my very light knowledge of the technology, that you have, like, a single direction, ability to increase the size, of the pattern. Of course, you can only increase it, you can get it smaller. Is that the right way to think about, you know, which layers are going to be more challenging for the technology to be adopted? Would you be able to give us an example of a specific layer that would never be a candidate because the size of the features are too small, or like, elongating in only one dimension is never going to make it work? Is everything potentially a candidate? Yeah, it's a good question. In general, I think every layer is a candidate. Yeah, there's no real limitation. Like I mentioned earlier in a different question, there are some customers with certain patterning layers that certain schemes where it's not so straightforward to implement pattern shaping. You know, it's not simple, there's always the opportunity to rethink the scheme for those layers. You know, this is a brand-new technology, so all of our customers have been marching down their roadmaps without this capability. You know, everyone's roadmap from the beginning doesn't include it. Once you have the capability, you know, our customers. From the beginning of a node, say, for example, if you know you have this capability, you can start to think about what's the best patterning schemes, you know, and best ways to take advantage of pattern shaping. Yeah, I don't think there's any layer that. There's no feature size too small or a size limitation or anything like that. It could be applied to any, it's just some are easier than others. When you say, easier than others, it means there is, like, a kind of a redesign kind of work, like changing the way you design? Exactly. Adapt it. Exactly. That's very clear. Okay, thanks very much. Yep. I had another question on, like, the field of application of the technology, because today, you've presented it as you can basically remove your patterning layer and replacing by a single patterning layer. Another way to think about it is to say it's enhancing a single patterning layer. Absolutely. In this way, would you be able to enhance a dual patterning layer? Imagine that, in a couple of years from now, some of our clients are going to introduce a kind of like artificial, like, triple patterning EUV, where you have actually on two patternings, plus, the shaping on the back of that. Is that the right way to think about? Absolutely you explain usage? Yeah, it's absolutely the right way to think about it. Like I mentioned earlier, you know, eliminating a EUV layer is just a very compelling value statement, that's where the early adoption is. There are, you know, dozens of ideas of different ways we can, like you say, enhance a patterning capability or even create device structures that aren't possible to be created otherwise. Lots of ideas we have for other applications that I think will come down the road when our customers get comfortable with the technology. There's probably, you know, dozens more that we haven't thought of yet. You are thinking about it the right way, yeah. Thanks. One last question, maybe a bit of a stretch. When I look at the picture of your tool, I see you have, like, one chamber, and then you have four units around the chamber. Yeah. Are you going through, like, four integrated process steps to achieve that, or is that just splitting the workload across? Yeah, yeah. Four units? It's a good question. No, there are not four separate kind of process steps. It's just the same kind of chamber replicated 4 x, just purely to get, you know, as much productivity out of a small footprint. It's just clustering four identical systems. You could just have one, Right. Do the same job, yeah. Excellent. Thanks a lot for the session. Very interesting. Yep. Great. Yeah, thanks, Pierre. I'd like to take a writing question from one of our buy-side analysts on the East Coast. The question is that, EUV is here, but high-NA EUV is coming. One of the benefits that we're hearing about with high-NA EUV is that it can replace EUV double patterning. Therefore, is the Sculpta product something that has a relatively short lifespan in the industry, or is it not obviated by high-NA EUV when that comes in? It's another good question. For sure, High-NA, you know, improves resolution, it enables smaller dimensions, and it's gonna mainly be used to shrink pitch. One thing it doesn't address is this tip-to-tip trade-off. As you squeeze pitch, it will continue to be, you know, more and more difficult to pattern tight tip-to-tip spacing. We think, that, you know, Sculpta will be applicable for High-NA layers just as it is for low-NA. Okay, great. Thanks, Steve. Yep. Our next question will be from the audio queue. I have a question from Atif Malik from Citi. Atif, can you hear us? Yes. Mike, can you hear me? Yes. Hi, how are you, Atif? Hi, thanks for doing this, and it does sound like a very big deal. Mike, I was at SPIE yesterday, and I could not help notice how much time ASML CTO spent on the need to improve the productivity of EUV for double patterning and multiple patterning, you know, at least through the high-NA. All this stuff does make a lot of sense directionally. My question is on the memory side, on the DRAM side. Are there applications or steps where the EUV steps for the DRAM devices can be replaced by Sculpta? Thank you. Yeah. Right now, we aren't focused on memory. I think as memory starts to implement EUV and then maybe get into multi-EUV, then the same applications will appear. I will say we've done a little bit of work with memory customers, just identifying, you know, non-mask elimination applications. Kind of like what Pierre was saying earlier, just ways that we can enhance existing patterning, even for 193i. So the applications are there. I think they'll be there in the future. It's just a, you know, question of value capture. That's all I had. Thank you. Yeah, okay, thanks, Atif. We have a question on the line from Brian Chin, who's with Stifel. Brian, we're gonna invite you to unmute your line. Hi. Hi there. Can you hear me okay? Yeah. Hi, good morning, Brian. Great. Thanks again for this presentation. Maybe just a couple quick things. You referenced a $350 million capital cost in terms of the, you know, the second EUV workflow, and a $250 million cost savings, so that residual is a $100 million. And, I guess, can you break out sort of what's in that $100 million? Obviously, the patterning maybe is the highest value add of that, but there's other things like cleaning and metrology, and how can you kind of help us understand how you share in that value creation of that residual? Yeah. For the model, we use. You know, we have an internal model for the lithography step, which is, you know, where most of the savings are. We use kind of generally accepted numbers for lithography ASP and productivity. Certainly, it the lithography tool is the biggest chunk of it, but all the other steps that are eliminated are significant. They're, you know, they're all important part of the savings. Steve, if you don't mind, I'd just kinda add in there, when you look at the adoption of Sculpta, it probably does not change the metrology intensity. You know, you're obviously doing a patterning step, and you have to go in and verify the pattern, whether the pattern's created by the second EUV step or it's created by Sculpta. From our perspective, I don't think our customers would save anything in their metrology budgets with this technology. Yep, that's right. Yeah. Okay. And, I imagine this, there's also I don't know if you can quantify this, but a significantly tighter footprint that this workflow would create, replace relative to what... Sure. Yeah, absolutely. That's part of. The entire workflow would have. Yeah, that's right. That's part of the model. Yeah. Yeah, does that make it even, you know, for, say, greenfield facilities, in terms of being more, you know, customers being more thoughtful? Is that? Given the potential productivity enhancement of just fitting more tools, you know, in a given amount of real estate, is that something where this is even more ripe for, like, greenfield facilities that haven't yet or are being constructed? I'm not sure I would say it's more ripe for it, but you're thinking about it the right way. It's if you're designing a greenfield fab, it just, it saves a lot of cost. Yeah, when you think about we, you know, we have our ESG commitments and program, and, you know, one of the things that we've endeavored to do is we wanna save, you know, we call it 3x30, so, 30% reduction in electricity usage, 30% reduction in materials, and then a 30% increase in footprint density because the, you know, the clean room and all of that, you know, is real energy intensive as well. That's half the energy used in the fab is below the clean room. This tool could actually help customers to meet their environmental goals as well. Very, very last question: Is the lead time for this tool less than the two-year lead time for EUV? Yes. Yes. Yeah, it is. All right, fair enough. Yeah. Thank you. Okay, thanks, Brian. I'd like to go back to the next question, and that's gonna come from Joe Quatrochi, who's with Wells Fargo. Joe, we're gonna invite you to unmute your line now. Yeah, thanks for taking the questions and doing the call. It's really helpful. I just wanted to kind of go back to the point on High- NA. I just want to understand, so I guess it seems like this product is trying to kind of maybe intersect the same kind of timeline as High- NA coming into the high-volume manufacturing. Is that the right way to think about it? From the discussions you've had with your customers, does that change the way that they're thinking about implementing High- NA? No, I don't think that's the right way to think about it. The, you know, High- NA is a few years away, and customers are adopting Sculpta now. I wouldn't link it to High- NA, and I would say I don't think Sculpta has any effect on High- NA adoption. I think they're independent. Like I said earlier, Sculpta is applicable to Low NA, High- NA, equivalently, and for customers to adopt, they're adopting High- NA for different reasons than they would adopt Sculpta. Okay. Yeah. Yeah. Got it, got it. That's helpful. Yeah. Thank you very much. Yep. Okay, thanks, Joe. We have a question on the line from Quinn Bolton, who's with Needham & Company. Quinn, can you unmute your line for us? Okay, I'm not hearing a response from Quinn. Let me just see if we have another caller, Timm Schulze, from Redburn out of the U.K. Timm, are you on the line and able to unmute? Can you hear me okay? Yeah. Hi. Yeah. How are you, Timm? Hey, I'm well, thank you. Thank you, Mike, for taking my question. I had two. The first was, you mentioned that you've been selected as process tool of record, that you are shipping for production. Just wanted to understand when you would expect that to start shifting into volume manufacturing. When will you get a real production volume test of this technology? Yeah, that's a good question. I think it's, you know, that, again, sort of depends on our customer and how well they execute. Probably, yeah, on the two years kind of timeframe, roughly. Got it. Got it. My follow-up question was one around risk. You know, there's obviously a general risk aversion within the industry. Yeah. Are you sharing any commercial risks, any financial risks with your customers around adoption? As you think about how this might be moving into volume production, would you expect the customer to maybe run it in parallel with double patterning, and then kind of dial down one and dial up the other? Just kind of how should we think about that happening? Thank you. Yeah. First part of the question on risk is nothing out of the ordinary and, you know, we're not sharing risk in any different way than we would for any other product. In parallel, I, again, I can't really speak for the customers and what they're gonna do, but I wouldn't expect that. All right. Thanks very much. Yeah. Thanks, Timm. We're getting quite late in the hour. We've overrun a bit. What I'd like to do is just pull two analysts who've not had an opportunity to ask a first question and see if they're still on the call. Quinn, I'm gonna come back to you and see if you're still there, and if you can unmute. Quinn Bolton? Yeah. Can you hear me okay? Hi, Quinn. We can hear you now. Thanks. Hi. Yeah, I just wanted to come back and ask on the High-NA, why this doesn't potentially push out an option of High-NA? It sounds like the answer is that this improves tip-to-tip spacing but doesn't improve the pitch resolution. So if you want to improve pitch, you've got to go to High-NA, then you get the advantages of Sculpta on tip-to-tip. Exactly right. The two aren't exclusive, they're complementary. Exactly right. Yep. Okay. Okay, great. I just wanted to make that clarification. Yep. Thank you. Okay. Thanks, Quinn. Finally, I'd like to go to the line of Tammy Qiu from Berenberg in the U.K. Tammy, are you still on the line, and would you like to unmute for us? Okay, you guys hear me? Yes, we can. We can. Okay, amazing. Thank you. My question is about when going forward, when you move from things like 3 nm to 2 nm around, at some point below 1.4 nm, you probably have to do CFET. How does this tool work with the further adoption of NA and High-NA? Does it work well as it is described today, with the transistor kind of patterning method changes? Also, another question is, when we actually talk about this tool is making double patterning easier, can we actually apply this back to the older node? i.e., for example, if someone today is working on 10 nm but really wanted to go down to 7 nm, can this tool be kind of re-engineered to make immersion-based double patterning easier? I might have lost track of all of the different parts of the question, but I'll start with the older nodes. Yes, it theoretically could be applied to older nodes. It could be applied to 193i layers. There's nothing stopping anyone from doing that, and you would see the same kinds of application advantages. You could eliminate layers. Just the value there is lower, you know, so it's just a question for the customers, whether it's worth it for them to bring in a new technology and, you know, disrupt a something that's already working well for them, but there's no reason you couldn't. The High- NA question, I think we talked about it before, but this is Sculpta and pattern shaping is just as applicable for High- NA as it is for low NA. High- NA will suffer the same kind of tip-to-tip problem that low NA does. The logic of the tool works the same as we move to different transistor type, i.e., for example, if CFET will be adopted? Yeah, that's right. Yeah, it's a good. We get a lot of questions about different device types, gate-all-around, CFET. This is a patterning tool, so, you know, the patterns are sort of generic, especially, for example, in the wiring, the interconnect wiring is all the same, and then even in the device patterning, contact patterning, you know, we're just making shapes on wafers. What's done with those shapes and what device structures you end up with afterwards is sort of independent. Okay, last one, I promise. Does this tool help with multi-patterning or quadruple patterning besides double patterning as well? Sure. It could absolutely be used for, you know, especially in 193i and the later stages of using 193i, there were some layers that required, you know, many exposures, three, four, five, six, seven exposures of 193i to make one pattern. For sure, pattern shaping could help, you know, take away one or two of those layers. Okay, thank you. Thank you, Mike. Thank you, Tammy. We do have some follow-up calls in the queue. What we will do, we'll close the call now, but we'll send an email to each of you and see if we can help you offline today as soon as we can find you. What I'd like to do is thank you everybody for attending and giving us your great questions. I'd like to as well thank Steve and Keith for your presentations today and for helping us to answer all the questions. If anyone still has a question for the Applied team, please just send an email message to either michael_sullivan@amat.com or martin_parker@amat.com, and we'll get back to you today. Thanks for joining us today, and have a great rest of your day.