All right. Good morning, and I guess, good afternoon to some of the folks. I'm Ross Seymore. I head up semiconductor research here in the U.S. for Deutsche Bank, and we're really pleased today to host a brief webinar with some of the management team of Broadcom. The topic today will be success in custom silicon accelerators. Really hot topic in semiconductors these days. Custom silicon, ASICs starting to penetrate a wide array of end markets, cloud, telecom, et cetera, and some others. The logistics for today's meeting will be, I'll do a little introduction, then we're gonna hand it over to Broadcom. Hock will have some introductory comments, and then we'll hand things over to Frank Ostojic. He's the SVP and general manager of the ASIC Products Division. Then Frank will hand it over to Vijay Janapaty. He's the Vice President and General Manager of the Physical Layer Products Division. Then after that, we'll go into Q&A. The presentations from the Broadcom folks will last about 40-45 minutes, and then we'll go into Q&A for 30-45 minutes after that. For the Q&A, we're not gonna do the hand-raising thing that we sometimes do on Zoom. If you have questions, and we very much encourage you to ask questions, please email them to me, and I will ask the Broadcom folks your questions. You can email me at ross.seymore@db.com. That's S-E-Y-M-O-R-E @db.com or you can Bloomberg me. Either way, those will work, and I'll ask the questions. If you want the question asked to a specific person at Broadcom, just put that in the question as well. Finally, on logistics, hopefully you can all see the slide that's up on your screen. If not, in the upper right-hand corner, you can click on the view button and change the view to see the speaker or the slides or however you wanna do it. With all those logistics out of the way, why don't I pass it over to Hock Tan, the CEO of Broadcom, to kick us off. Hock? Well, thank you, Ross. Hi, everyone. I'm pleased to be here today to talk about Broadcom's custom silicon business, its evolution, and our future opportunities. I would like to highlight that our long journey in developing very successful custom silicon for very thoughtfully selected customers, I should add, comes from our access to proven silicon technology, very robust methodology, and for us, a very unique set of skills, even as today, the laws of physics are starting to become a headwind in the semiconductor industry. Today with me, we have Frank Ostojic of our ASIC division and Vijay Janapaty, physical layer products, who will both discuss how Broadcom drives success as the undisputed leader in custom silicon. Next slide, please. As always, at the risk of being repetitive to some of you guys who have listened to our teachings, particularly last year, various teachings of Broadcom. Let me reiterate our business model clearly. As you know, we did not get here overnight where we are. In fact, since we began back in 2006, we have been carefully acquiring solid businesses and expanding our platform from 8 then to 22 product franchises, and most importantly, reinvesting to grow these businesses. Now, each of these category-leading franchises, as we call them, have three common attributes. First, they have to have mission-critical technologies that ensures a sustainable end market. Secondly, we are the technology leader. Finally, we have the leading market share in each of these verticals. You'll hear today how our ASIC business fits very squarely within this criteria. The financial outcome of this business model I just articulated is very real. Since our IPO in 2009, I show you in the charts, our revenue on the left side has increased 19-fold to $27.5 billion last year, 2021. R&D grew 24 times over the same time. Over the same timeframe, operating profit grew 177 times. As I've always said, the semiconductor industry is a very deep profit pool. Many of you keep asking me, how long can this game go on? Particularly so in the context of an industry shown here that's seeing Moore's Law coming very much to an end. To explain, on the left, physical scaling of transistors has flattened out, shown here clearly. Meanwhile, on the right, power density measured by watts per square millimeter continues to rapidly grow. In other words, putting all this in simple language, we cannot increase chip semiconductor performance by just putting in more transistors into every square millimeter of silicon die. We saw this first in 16 nm process, and since then in each subsequent generation of 10 nm, 7 nm, now 5 nm, and we will see it in 3 nm. Where does this take us? Well, to pause here and think a second. Over the last 20 years, digital transformation, as we described it, has been progressing very well rapidly, driven by increased complexity, I might say, of workloads and software. Measured, to the extent we can measure it, at 1.4 multiple every 2 years. However, over the last 5 years, demand by such software workloads has accelerated to over 15 times with the advent of AI and machine learning workloads in real time, in particular. Over the same time frame, as I mentioned above, performance in computing hardware has actually slowed or flattened. No more than 2x over the last same five years. For the semiconductor industry, the advance into deeper submicron process node is no longer sufficient. New approaches to system and chip architectures have evolved. One path, you know, taken by hyperscale players in particular is to simply offload workloads from general purpose computing to domain-specific silicon accelerators. Not my words from Google. That's true. Said another way, we're just simply converting software back to custom silicon. The other path, which we at Broadcom is pursuing actively, is to leverage the process improvements in deep submicron CMOS silicon and migrate discrete building blocks of analog non-silicon components into custom SoCs. Here's a passing thought: Are the limits to Moore's Law then truly a negative for the industry from a financial point of view? Or is it ushering in a new era where silicon consumption may actually grow as chip architectures scale out horizontally and more than offset the decline in general purpose hardware? Who knows? With that, we might actually see an uplift in the industry's historical 5% growth trajectory. Clearly, the recent growth in our substantial and growing custom silicon revenue supports this hypothesis. With that, I'm pleased to turn the presentation over to Frank. Frank. Thank you, Hock. Good morning and good afternoon to some of you. My name is Frank Ostojic, and I'm gonna be talking about the custom ASIC business and our capabilities. Later, Vijay will be talking about the applications that we serve in with this business. As Hock mentioned, we are investing $5 billion in R&D. A large portion of these funds are invested in IP cores. These IP cores are not only used for our standard products, but also our IP is available for us to build custom ASICs. Our large scale of IP investments offers us two distinct advantages. Number one, it allows us to invest in many IP cores in parallel. Number two, it allows us to move our IP cores quickly and early to a new process technology. Next slide, please. Like Hock said, where did this business come from? This is not something that showed up overnight. The road to becoming the leader in custom ASICs was difficult, and it was long. We survived it, we persevered, and now we are fortunate to be the leader in this segment. Our custom business was built up carefully and methodically over the past three decades. In the beginning, we had to compete with IBM Microelectronics, with ST, TI, and others. With discipline, good products, and focused IP investments, year after year, we're able to win more and more projects. Custom ASICs is a tough market. Many companies have tried to gain scale in this market, and they have come, and now they're gone. We were able to outlast our competitors. It took us many years to earn our leadership position. You might recall this diagram from previous presentations, and this shows all the acquisitions that resulted in the Broadcom of today. As part of these acquisitions, we merged three of the world's leading ASIC groups into one. First, LSI was the leader and pioneer in ASIC design. Vijay came from LSI. LSI and Agere ASIC group merged in 2007, as you can see in this diagram. LSI brought with them many customers in networking, in wireless infrastructure, and in storage. I came from the HP side. Back then, my team and I were building ASICs for HP compute and networking groups. In fact, today we've continued to build HP latest compute and networking ASICs. When we combined the LSI team with the Avago ASIC team, we increased our scale for both ASIC and IP design. Subsequently, as you can see here, the acquisition of Broadcom significantly increased our scale in IP cores and IP engineers. Since then, year after year, we steadily increased the number of customers and projects. These mergers, together with a gradual organic growth, created an unmatched scale of engineering, methodology, IP, and a very solid customer base. We have developed a culture that delivers value on our customers, and through this we have created a franchise that has earned a strong position of incumbency with customers in these markets. We remain agile and awake. We paid a close attention to the technology trends and changes, and we were able to move from growing market to growing markets. In the ASIC market, it is imperative to choose your customers carefully. We have been selective, and we have partnered with customers that are the leaders or that have the right momentum to become the leaders in their respective markets. In the past few years, we worked closely with several data center leaders to create custom solutions. The end of Moore's Law has played to our favor, especially in the compute offload market. The need for custom devices for dedicated workloads has enabled us to partner with several data center leaders to design TPUs, video accelerators, DPUs, and other devices. Later in the presentation, Vijay is going to share more details on the applications we serve. Next slide, please. Okay. In the ASIC business, talk is cheap. Revenue, revenue and scale are what counts. Here is the revenue that we have achieved. I'm showing in this chart two of our custom segments. On the left, I am showing the custom switching and routing revenue. On the right, we are displaying the revenue for the compute offload ASICs. Both segments have grown as a result of years of disciplined investing and years of good execution on the design wins that we have earned. You can see that the growth of compute offload ASICs has accelerated significantly since fiscal 2016. Next slide, please. Now in this chart, you can see the 10-year revenue with both of these segments combined. Our scale, our IP cores, and our unique engineering skill set has enabled us to grow at a CAGR of 20% over the past 10 years. You can see our revenue for fiscal 2021 for this combined segment was north of $2 billion. Next slide, please. All right, so let's talk about IP now. Broadcom's $5 billion in R&D investment enable us to have a broad set of IP cores and fund many experienced engineers. This gives us the scale to work on the broad silicon IP that I'm displaying in this slide. We do not work on this IP core serially. Instead, we work on them in parallel. We also move them to the next technology node in parallel. We are the leaders in SerDes technology. To be successful in ASIC, it requires more than just SerDes. We have all the needed cores for signal processing, connectivity, memory protocols, processing, computing, et cetera, et cetera. This vast library is open for our customers to build the most advanced custom chips for their applications, whether they're in data center, enterprise, wireless infrastructure, et cetera. Moreover, it's available for them to use in the most advanced silicon technology node. Our IP library is one of the reasons we have added more and more customers and more and more products. Next slide, please. Now let's talk about cadence, talk about timing. Our scale of IP and ASIC engineers allows us to be the leaders in silicon technology generation after generation. See in this chart that our scale in Broadcom enables us to tape out more than 200 chips a year. That is the scale that gives us a huge advantage. Next slide, please. All right. Now I'm gonna start digging in on what is this. What is this? This is a machine. That's what we have created. We have pre-created a predictable ASIC machine. We carefully created an automated ASIC machine. Over three decades, we have designed and perfected a software-based automated method and flow to design chips. We call this flow and methodology the ASIC machine. The premise and the goal of this ASIC machine is the following. Number one, predictability. Number two, time to market. Number three, quality. Number four, engineering efficiency. Let me explain. What we do is we take our ASIC machine flow that we have built over four decades, and, for example, in 2018, we port this ASIC machine from 7 nm to 5 nm. Then we use it in this 5 nm ASIC machine flow in the first 2 to 3 chips, and we naturally find problems and inefficiencies. We fix these problems, we eliminate the inefficiencies. By the time we're in the fourth chip, we have an improved flow that is fully adapted to 5 nm. Then we use this proven flow for all the rest of the chips. Whether we're doing those chips in California, here in Colorado, in India or Europe, we use the same proven flow with our proven IP. Our flow is flexible. It can allow us to work on small chips as well as large complex chips such as TPUs. In every generation, we enhance the flow, we make it faster, and we make it more efficient. Let me discuss more in depth what this discipline in the ASIC machine enables us. Number one, a reliable, predictable schedule. Our customers love that, and that generates trust. So our customers come back to have the same predictability for their next program. Number two, we enable our customers to have a time-to-market advantage with the latest silicon technology. This allows our customers to add more content and to lower their power consumption per function. We give them a low-risk path to have a design with the best IP in the most advanced technology available. You can see this is one of our calling cards. Number three, quality. Since we're using the same proven flow for 20, 30, 60 or more chips, we inherently ensure quality. We're taking a customer chip over a paved road instead of doing a live experiment with their design. Again, this creates customer loyalty and creates a strong position of incumbency. Number 4, last but not least, this ASIC machine creates an unmatched engineering productivity and efficiency. Thus, we can increase the number of projects that we do and increase the number of customers we serve. The increase in number of projects brings revenue growth with a manageable investment. Additionally, the IP we invest is not only used for our ASIC customers, but is also used by our other 17 standard product divisions in Broadcom. As you can see, this is truly a machine. You can see that we have more than 20 designs in 5 nm, and we already have 10 designs in development in 3. These numbers are growing every month. Now, due to the inherent complexity of chip design in advanced nodes, it's not possible for a company to reach efficiency and quality when they're doing just 2-3 chips per node. It takes 2-3 chips in each technology node just to find the basic problems and to try to fix them. By the time a company gets to a semi-proven formula to build chips in a given node, it's time for them to move on to the next node or the next architecture. In this industry of custom ASICs, it is imperative to have scale and continuity so that you can create leverage, efficiency and quality. With our scale in Broadcom, we've been able to perfect this ASIC machine, and we leverage this investment and methods for 50-90 chips with the same platform. No ASIC provider in the industry has this scale, this continuity, this efficiency, and this predictability. Next slide, please. Let's talk a little bit about what we can get done in the methodology. Our discipline in advanced engineering have not only enabled us to have scale, but also they enable us to tackle the most complex custom chips in industry. I have a couple examples here of two chips that we are ramping in production in 5 nm. These chips are designed in complex 2.5D packages. Each one of them has several HBMs, which stands for high bandwidth memory. They have cores of 60 billion-110 billion transistors. The die sizes are 600-800 square millimeters. These designs have embedded 100-Gig SerDes, and soon to be 200-Gig SerDes. They have the latest HBMs, chip-to-chip IP, ARM processors, the latest PCI Express, et cetera, et cetera. Next slide, please. Okay, how do you put these chips together? That is packaging technology. To design this complex data center ASICs, it is necessary to have the most advanced packaging technology. We have invested in the IP, also in the mechanical, thermal, and electrical technology that ensures the systems in a package are reliable. Our packaging technology enables us to integrate up to 60 die in one package. We invest in these packaging platforms long before they're needed. These are very difficult systems to prove and to design. Our designs and qualifications ensure mechanical, thermal, and electrical quality. You can imagine one mistake can create cracks, delamination, thermal issues, et cetera. There are thousands of connections in these packages. There are multiple layers. It takes the right engineering expertise and the learnings from previous packaging generations, as well as a large R&D investment to ensure these packages are ready for high volume production. In these slides, you can see how we are growing the capability in packaging size, as well as enabling more complex die stacking by going to 2.5D and going into 3D packaging. Hopefully, this gives you an idea of the capabilities and the results of our ASIC machine. Now I'm going to give the time to Vijay, who's going to dive into the applications and markets where we're using our technology and our scale. Vijay. Thank you, Frank. I can go to the next slide? Yeah. Allow me to provide some application examples for hyperscale silicon accelerators. As Frank mentioned previously, we are in the middle of a large secular trend to offload software complexity and general purpose CPUs and GPUs to domain-specific accelerators. These accelerators are implemented often as custom silicon or ASICs, and this secular trend is driving the growth for custom silicon. In the next slide, I will start with AI custom silicon example. The largest and earliest example for offload is for artificial intelligence. AI started with offload from CPUs to graphic processors or GPUs. As the demands on AI models increased, it has now become imperative to offload GPUs to custom AI silicon to realize commercially viable solutions. Custom AI silicon consists of 1, a large array of matrix multiplication and accumulation functions, and Broadcom implements this array with custom cell libraries and SRAMs in 5 nm or 3 nm. 2, Network connectivity is critical in AI systems for communication between nodes and the backbone networks. This is implemented with 100 Gig SerDes links, primarily over direct attached copper. Broadcom's 100 Gig SerDes is an important ingredient in realizing cost and power-optimized networks. 3, Broadcom's unique die-to-die interconnect with bandwidth greater than 10 terabits per second is used for partitioning the silicon and mixing die from different process technologies. 4, HBM2E or HBM3 provides the required bandwidth and capacity for AI workloads. Broadcom partnered closely with Samsung to realize high-quality SoC solutions with integrated HBMs. 5, as Frank mentioned, advanced packaging technologies like the TSMC CoWoS and advanced substrate technologies are critical for packaging these training and inference ASICs. Broadcom partnered with TSMC in proliferating 2.5D across AI and other applications. 6, Broadcom ramps these products into production within 6 months from sampling. In summary, Broadcom's best-in-class IP cores in a leading technology node, our differentiating design methodology, advanced packaging, and flawless execution enables aggressive time to market. This time-to-market advantage is critical for hyperscale customers. In the next slide, I'll cover the benefits of custom AI accelerators and our design wins. As I mentioned previously, GPUs are offloaded to custom AI silicon. The illustration on the left on this page shows the performance gain for custom AI ASICs like Google's TPUv4 versus NVIDIA's A100 GPU-based systems. Custom silicon-based AI systems like TPU v4 provide higher performance, have much lower power, are 20%-30% lower in die size, and can be built with reduced interconnect costs. These chip and system-level benefits translate into faster training times and a substantial reduction in CapEx and OpEx for our customers. Hyperscale customers optimize silicon for AI workloads to suit their application use cases. In 2018, Broadcom had 3 AI ASIC programs in production. Now there are 9 programs in production. Our design wins and revenue is growing rapidly, and adoption of custom silicon for training and inference is accelerating among hyperscale customers. We are leading the industry in enabling this proliferation. In the next slide, I will cover other data center accelerators such as SmartNICs and video accelerators. Software complexity in the modern data centers, as Hock mentioned previously, continues to grow dramatically. Hardware accelerators such as DPUs or SmartNICs and video accelerators have absolutely become a necessity. Such SmartNICs or DPUs and video accelerators are built as custom silicon and are tailored by customers towards workloads for their business model needs. These ASICs include functions such as, 1, offload for virtualization, security, protocols, data center orchestration, and more. 2, offload of video codecs for transcoding use cases. These ASICs consist of high-bandwidth memory, high-speed DDR interfaces for required memory bandwidth and capacity for buffering. 4, multi-core high-performance ARM subsystems provide the necessary processing capability. Last but not least, and 5, high-speed network connectivity and security is enabled over multiple 800 Gig Ethernet links. SmartNICs or DPUs and video accelerators provide significant benefit in offloading virtualization, protocol, security, video, and enhanced data center orchestration. Broadcom enables an aggressive time to market with best-in-class IP in a leading node, a differentiating design methodology, advanced packaging, and high-quality manufacturing. Next slide, please. I'm now gonna switch gears and provide some application examples of how Broadcom is driving innovation with horizontal integration. Horizontal integration is the integration of adjacent chips in the signal chain. Discrete analog functions implemented in non-CMOS or even older generation CMOS are integrated into a custom ASIC implemented in the leading-edge process technology node. Integration of discrete analog functions is the holy grail for designers and separates men from boys, so to speak. Broadcom has a rich portfolio of analog IP and capabilities such as ADCs and DACs, regulators, linear drivers, amplifiers, and much more. Horizontal integration increases Broadcom's content and drives revenue growth for custom silicon while providing power and system cost benefits to customers. In the next slide, I'll show you the 5G Massive MIMO radio SoC example. Massive MIMO radios are necessary for expanding capacity and coverage and enable widespread use of 5G. Penetration of these 5G radios is contingent on realization of solutions that reduce CapEx and OpEx for the operators, as well as enabling new use cases such as factory automation. Current radio solutions use multiple digital front-end ASICs and discrete data converters as shown on the left. With the integration of all these chips into a single SoC in 5- or 3-nm, we enable several benefits. 5G advanced support up to 7.125 GHz for unlicensed bands enables new use cases. High bandwidth of 800+ MHz per transceiver. Dual band support on every transceiver, enabling aggregation of the spectrum. 25% or more reduction in power and board space for combined digital and analog front-end, thereby reducing antenna size and weight. Our SoCs are highly software programmable and enable OEMs and service providers to reduce radio hardware SKUs. With a unique horizontal integration approach, we enable significant CapEx and OpEx reduction for the operators. Next slide, please. Please allow me to provide some more details. Broadcom partners with wireless infrastructure OEMs on these cutting-edge radio front-end SoCs. These SoCs consist of, one, carrier aggregation, deaggregation, digital predistortion, crest factor reduction functions in a leading process technology node. Power efficiency is critical here. Two, Broadcom uniquely enables the integration of data converters into a single SoC. Broadcom is first to market with 5 nm direct RF converters, and these direct RF converters provide wideband capture, large bandwidth, and significant flexibility. These converters implement ADCs, DACs purpose-built for 5G and 5G advanced applications with 800+ MHz of bandwidth, support TDD and FDD use cases, and are highly configurable. We can either integrate into a monolithic ASIC or offer chiplet-based integration. Three, the die-to-die interconnect optimized for 5G SoCs provides high bandwidth and lowest power and reduces the power density. Four, 5G NR protocol and control plane are implemented in ARM and DSP subsystems. Five, baseband connectivity is provided with high speed CPRI or eCPRI interfaces. We estimate the market opportunity for massive MIMO radio SoCs to be north of $1.2 billion in calendar year 2024. In summary, integrated custom radio SoCs are mandatory to realize commercially viable massive MIMO radios with 64 TRX and more. Next slide, please. Here is another example of horizontal integration. Current industry solutions for 400 Gig and 800 Gig PAM4 modules in data center interconnect consist of discrete DSP, linear drivers and TIAs. These solutions have higher power and cost. Broadcom has a unique approach and integrates DSPs, linear drivers and TIAs into a single monolithic design in a leading-edge CMOS node. This integration eliminates the high power interfaces between the discrete devices and enables 25% power reduction. Broadcom solution currently enables 400 Gig modules with less than 7 watts of power and 800 Gig modules with less than 14 watts of worst-case power. We estimate the market size for these PAM4 DSPs to be north of $800 million in calendar 2024. We are currently the only company with a solution that integrates DSPs, drivers, TIAs, regulators into a single SoC for 400 and 800 Gig module application. Integration enhances the module yield, reduces the BOM cost and of course, power. With our unique approach, we are winning PAM4 designs, PAM4 DSP designs and are gaining market share. Next slide, please. This is my last example. We are designing custom coherent DSPs for high-speed transport and routing networks. Previously, these coherent PHYs were built with discrete DSP, forward error correction, ADCs and DACs. Broadcom integrates all these functions into a single monolithic SoC in a leading process node and with advanced power management techniques. Our ADCs and DACs are high performance with sampling rates exceeding 200 giga samples per second, and we lead the industry in the implementation of ADCs and DACs for coherent applications. We collaborated with customers and implemented more than 12 coherent ASICs, and several more are currently in design. These DSPs reduce power and size, and this reduced form factor allows solutions that span data center interconnect, wide area networks, transport networks and subsea networks. We estimate the coherent DSP opportunity to be $400 million in calendar 2024, and Broadcom is the number one coherent ASIC provider in the industry today. I will now conclude the presentation with the key takeaways in the next slide. The secular trend of hardware accelerators offloading software and general purpose CPUs and GPUs is a huge tailwind for custom silicon. Integration of discrete analog functions from non-CMOS or even older generation CMOS into custom ASICs drives content and revenue growth for custom silicon. Broadcom is the number one custom silicon provider in the infrastructure market, and our ASIC leadership is based on industry-leading breadth of IP cores, proven design methodology and a rich heritage of flawless execution. With that, I will turn the call back to Ross. Thank you, Vijay, Frank and Hock. Overall, like I said, if you have questions, please email them to me or Bloomberg them to me. I'm getting somewhat deluged with them, so it's great. We have a lot of good questions to ask you guys. Why don't I start, Hock, with a high level one for you. You've over the years talked about the challenges of being in the ASIC market versus the more general purpose standard silicon market. In the beginning of your presentation, you talked about the move to these custom solutions potentially accelerating the growth of the semiconductor market. How are we avoiding the substitution effect where the ASIC side would just replace the more general purpose and therefore it doesn't accelerate the growth? It might accelerate your growth, but it wouldn't do anything to the industry. Is there something that's incremental? Well, what has changed, perhaps I should answer your question a bit differently, Ross, is over the years, as hardware, semiconductor hardware outperforms our ability to complex using that verb as complex software workloads. It's not a problem in the sense that to go to more and more standard merchant silicon. Because what you're doing in effect by doing that is you're making your silicon simpler and easier to be programmed, flexible, resilient by writing software. In a way, software has been replacing, if you think high level, hardware. When hardware could run faster than software changes. Today, the opposite is the case. Software, basically, hardware cannot run faster than software, especially with real-time AI machine learning workloads. If you see how logical it is then that therefore take the thought and start converting software, which is what we call domain-specific, hardware, and make them into hardware. That's what is happening. In other words, the business or the whole process is going horizontal rather than keep driving down faster and faster silicon. Simply because the law of physics is telling us you cannot drive silicon any faster, the transistor when the building blocks semiconductors any faster. So build more of them. In doing so, you're replacing software with hardware, in effect, is how I would look at it topside. How does it work as far as replacing the merchant silicon side of things? Do you think the software replacement is larger than the, as you described it, merchant silicon replacement, so it still aggregates up to a positive? You still need a lot of merchant silicon because it's the default choice. By the way, in enterprise, it is, it has gone and continues to go very rapidly into standard merchant. It will go further and further into it, especially in the face of networking and even compute. When you start disaggregating software and hardware, as we are seeing more and more in our networking space, sure, people want flexibility. People want your hardware, your system architecture to be very resilient, elastic. The best way to do that is have merchant silicon. If you start making your hardware with bells and whistles, you got headaches running any hardware. Enterprises, however large scale enterprise, those big banks are, they are not geared up to handle this kind of situation. Only the hyperscalers would dare to approach creating domain-specific, custom silicon to replace software. The enterprise is still going very clearly in the direction of merchant silicon. If we talk about the growth rate of the market, the slides went relatively fast, but I've gotten a few questions about the growth rate from investors. If I recall right, you had a 20% CAGR on both sides of the equation, the compute offload side, and the routing and switching side of things. Given the dynamics you're talking about that are secularly changing, Frank and Vijay, feel free to answer this question too. But is that 20% CAGR something that you believe is accelerating going forward? Well, let me jump in and Frank will add in more. One, we may have kind of glossed over it too fast, but I tell you, if you look at the 2 slides closely, over the last 4 years, 3 years in switching and routing ASICs, it has flattened out. You see that? You measure it over 10 years, sure, you see, Moore's Law will tell you it's 20% CAGR. The truth is, over the last 4 years, it has flattened out. I dare say if we weren't on this cyclical super cycle, probably would be declining. ASIC in switching and routing is declining, flatten out at least. Offsetting it in our ASIC business is the sharp trajectory, if you look at over the last 4 years, where it's growing faster than 20%. When you net it out, we got an ASIC business which largely comprise net switching, routing, and offload computing growing at a compounded 20% over the last 10 years. If I look forward, do you think the compute offload side continues to accelerate and the routing and switching continues to flatten? Or are there some of the dynamics, Vijay, you talked about with the 5G side that will take kind of networking as a different term and re-accelerate that portion of the business? Yes. I think on the 5G side, I think we are very early in the innings on the growth. As you know, I think things are just starting out on that front. Yes, we will see the growth on the 5G front. Last high-level question, Hock, for you on the business model. You've said in the past about the merits and challenges of moving from merchant and the margin structure even holistically, nothing specific about these products. The margin structure being different on the ASIC side and custom side versus the merchant side of things. How do you allocate your resources accordingly if the merchant side is the side that generates more profit, but the customers clearly want to do more the custom side? How do you walk that tightrope? Well, Ross, before I jump into the depth of that question, let me also make sure we understand what I said about merchant silicon. As I said, switching and routing has flattened out and start declining. That's ASIC. Our merchant switching and routing is growing like gangbusters. It's gaining share over ASICs for the reason I mentioned about. Not every application wants to go into custom ASIC silicon, even among hyperscalers. It is only headed in that way in very specific applications where if you can run merchant silicon effectively, run merchant silicon. You don't need to do domain-specific silicon because it has higher risk. Then the question is how inexpensive or expensive it is, and which is your second question. As you see in switching, routing, people are not just telcos, hyperscalers, they have gone very, very merchant. They have been merchant very early on, continue to be merchant increasingly. Enterprises are going more and more merchant. I would say switching routing is definitely headed to a path where merchant will dominate that space. Now, in compute offload, which is very unique to hyperscalers, you pick and choose what you can do to be custom ASIC silicon, domain-specific silicon, so to speak. AI, as Vijay highlighted very clearly, is one space that makes plenty of sense because it's an architecture to be very optimal in doing an AI machine learning product chip architecture that you basically put in more tons of thousands, as many multipliers as you can squeeze in. You can make it extreme. The workloads, the software is very painful if you don't do it that way. Pure regression analysis. DPU is a questionable event. Might happen because it is starting to happen on DPU. Vijay also showed, we are also somewhat in it. Now, what we are seeing in compute offload in hyperscalers, to answer your question on margin, is very interesting. You know, you're trading software for hardware, and you can say software carries huge margin. But equally, from some other people's point of view, software is zero cost. So you see an extreme bipolar opposite. Suffice to say, we are basically Frank, in his ASIC division, earns pretty much the corporate average on semiconductor product margins. And that's where we are very thoughtful about the application we select and about continuing to invest in this space. The level of investment, to answer your last question, in terms of allocation, there isn't an allocation process across various product franchises. Every product franchise we have is given full liberty, and Frank included, Vijay included in physical layer products, to invest as much as they need, and maybe even more, to ensure sustainability of their roadmap and their position in the marketplace. That's it. Independent. We don't do actual saying, I support division A and I support switching versus ASICs. We don't do that. Frank does what he needs to do to sustain his business and is allowed to invest as much as he needs to run his business. Just one clarification to that answer you gave, Hock, is I assume when you say equivalent margins, you mean on the operating margin line? Because I know NRE and a bunch of timing of investments and revenue kind of screw up the gross margin line at times in ASIC businesses. That's correct. Great. A couple other questions on my side, and then we're gonna go the rapid fire route with no necessary rhyme or reason 'cause I'm getting so many questions here. On the competition side is one common theme. You can answer this at a high level or get as detailed as you wish. ASIC-specific competitors trying to do the same thing you're doing is one potential route of competition, so how are you seeing that? Is there any reason that your current ASIC customers, as they get bigger and broaden their own expertise, would be able to just disintermediate any of the semiconductor ASIC houses completely and do it themselves? and then finally, apologies for the complex question, there's a little bit of a bridge between those two, where there's some IT houses that are trying to provide individual blocks that could expedite those customers doing it themselves. How do you see the competitive landscape across those three different verticals? I'll let Frank take that question. Thank you, Hock. Yeah. Thank you for the question, Ross. Yeah, it is a very good question. It comes down to a choice of what the customer wants, right? If the customer wants to do a chip that's very complex, and it's very important to them to get it done really fast and to be the leaders in that area and beat their own competitors, then we come with the exact formula. We come with something really proven, something that can guarantee that their service is gonna work, their packages are gonna work. They need to worry only about their architecture, what they wanna do, and we give them a paved road. Of course, if the customer says, like, Hey, I want to do it on my own, then they're gonna have to figure out how to do that, and then have to do it a little slower and then get there maybe a little later, and that might be pros and cons on that approach. In terms of competitors, right, Vijay and I have grown up in this business with competitors, right? There are competitors that come, competitors that go. We know how to deal with them. We know how to invest. We know how to take care of our customers. It's something that we're prepared to continue to do. Ross, if I could add on a high level. As Frank was at pains to lay out his business model, his technical model in ASICs, there's a lot of barriers to entry in doing ASICs. It's not someone showing up one day and saying, I'm going to do a chip in 5. As Frank said, But you haven't done really much in 7. What makes you think you can do it in 5 nm? I'm talking particularly to some competitors or hopeful competitors who say that. It doesn't. It's continuity. You do 7, and when you do 7, you learn from doing 10. When you did 10, you learn from doing 16. Just to do 5, you better have done 7. There is continuity and what they call sustainability. You just can't show up one day and do one. There are lots of barriers to entry in this industry, much as it may not seem so, and Frank outlined it very clearly. Each of them is necessary, maybe not sufficient, to win in this space. I guess the best way to describe it, we believe we have you know the highest levels of performance capabilities and which is why I use the word, we have very differentiated and unique set of skills in being so successful in the custom silicon business for the last 10, 15 years. Not the last one or two years. We basically have outlasted people out there who were household names long time ago in the ASIC industry and who are no longer around or who may morph into a different name under different situation. It's not that easy a business. The best comparable I would use to some extent foundry. Not poking at anything. TSMC as a foundry, the world's largest, by far predominant wafer foundry for the industry, did not get there overnight. It was created. It grew over 20, 30 years. The kind of things TSMC does for the customers of theirs in the industry. It's more than just technology. It's a set of skills that invest in the culture of the organization the way they partner with key customers. Question for Vijay and maybe for Frank as well. The time to market from when the engagement begins to when the revenues come. Vijay, you gave a couple of the case studies for some of the integration you're gonna do on the 5G side of things. How long does it typically take from engagement to revenue? And does it differ significantly between the two primary markets you're addressing? Yeah, I can take that. There is a difference, right, in that. I think how we measure that is in custom silicon, you know, when the customer is kind of ready with their architecture, right? Their so-called algorithm that they want to implement. I think we actually pay a lot of close attention to how fast we can take that into tape-out. As I was telling you in the presentation, we are typically ready to go to production within 6 months of having the sample, right? In the hyperscale situation, the ramps are very fast, right? From the time the customers are ready with their algorithm or their so-called final architecture to how we ramp is within 18 months. On the telecom side, there is a little bit more delay. I think, you know, there are lots more tests that need to be done. As you know, they need to be field tested and things like that. There is some delay there, but usually we are ready on our side to ramp into production to enable field tests, and then it goes into production. There is probably another couple of quarter delay in the case of 5G or telecom use cases. Ross, let me add a couple of things there. Let me give an analogy. Our business model in a way is like, you know, we work with a customer to build a custom car, right? The customer brings their engine, the architecture. That could be inference, that could be training, that could be 5G, you know, algorithms, that could be routing algorithms, that could be switching algorithms, that could be DPUs, anything. They bring the engine, they bring their secret sauce on how they wanna do it. It's like we build a Ferrari, we put the wheels on, we put the chassis, we put the, you know, the steering wheel, we test the brakes, everything is ready. We just connect the engine and hit the gas. That is the analogy, right? That's what we offer to our customers. We have a Ferrari ready for them to put an engine. The engine is Their secret sauce, where they want to differentiate themselves from their own competitors. We provide them the ability to just put the engine, hook it in, and hit the gas and beat everybody else. I got a question about the supply chain side of things. Not the shortages necessarily, but as you move into more horizontal integration, integrating those analog blocks, does your foundry partner network have to change? How able are you to ramp new partners that might have, you know, esoteric process technologies that are needed for some of that horizontal integration that you're doing versus the more pure vertical one where the leading edge is most applicable? Well, Vijay, you want to take it? Yes. What is unique in what Broadcom does is we don't go into esoteric technologies. We actually implement all of that integration in 5 nm, 7 nm, 3 nm mainstream technologies. That is really the trick, right? That's where we really differentiate. Ross, we may not have made it very clear, but it's definitely worthwhile to clarify what Vijay said. What we have in Broadcom within our organization, within our IP portfolio, but also engineering skills, is that regulators that take an esoteric process to do in bipolar BiCMOS or even switches for RF that does it in RFSOI or silicon germanium. Or as Vijay said himself on ADCs or DACs or analog digital converters or DACs, that very high performance, high speed that perform in some esoteric process in bipolar BiCMOS. We do it all in straight submicron CMOS. The implication is we then can integrate that core, that IP, that tech and that function into the SoCs we do. We have been doing it from all our SoC in merchant silicon for years and years. What we are highlighting here is we can do it just as easily for custom silicon in horizontal integration, but it becomes custom, as which is why we have not done it as much except in our standard product SoCs before. All the stuff you see, a lot of stuff you see in analog out there, whether it's clocking circuits, PLL, whether it's, you know, converters and, of course, SerDes is a mixing of parts. It's all totally can be integrated into straight CMOS silicon. That's what I think our horizontal integration to create custom SoCs now is just a manifestation of what we've already been doing in our standard silicon process. It's the technology we have, and we have had for many, many years. We just don't sell building block products. Thanks for that, Hock. One last final high level question, then I'll jump into some more detailed ones that again, may not have any rhyme or reason as far as one to the next, but I'm just gonna read off what the people are asking. The high level last one first is customer concentration. By definition, these are very large customers to be able to afford these engagements with you. How is the customer concentration currently, and how has it changed if you looked back a little bit and then as you look forward? We don't customer concentration is a big part of our business model, by the way, in semiconductors. Even in infrastructure software, if you hear a story on infrastructure software. We focus on the largest players in each of the vertical we play in, the franchises. It's like. Because we figure the winners are who we want to support. In semiconductors, 75%-80% of our total revenues comes from the largest 100 customers. Growing in this space with carefully selected ASIC customers will not change this dramatically. Great. All right. I'm gonna fire off some more direct questions now. One question was, does the move to chiplets make the increase or decrease your long-term competitive advantage? Yes, you have advanced packaging IP, but doesn't it make the overall process of designing a large chip easier, going to chiplets, especially if a particular chiplet could be held constant one generation to the next or even produced or purchased, I should say, by a third party. Generally, does chiplets create a bridge between the merchant side? Does it get around the scaling issue, and how do you view that threat? Okay, I will answer that then pass it to Frank in one sentence. Remember, real men do monolithic chips in semiconductors. How's that sound? Those who can't do monolithic chips will then start to sell you the idea of chiplets. Frank, your turn. Yeah. What we see is, we see both. We're doing some very, very large monolithic chips that have reasons to stay monolithic, and some of them could be architectural. We have some situations where we have IP ready, let's say in 5 nm, but we need to have a core in 3 nm that is very large. There we have the IP and everything for chiplets. In that area, chiplet has actually given us an advantage. I do not see how chiplets is going to hurt our business. In fact, I think we see it as a trend that's gonna help us because we're really good at connectivity. Then a little pivot to a prior question or a prior topic about SerDes. There's a number of companies have invested in SerDes IP, become pure plays in that regard. You guys have long differentiated by your SerDes capabilities. Do you see that advantage weakening at any point over time, considering there's kind of these standalone IP shops that some of your customers could go to? Or is the benefit of the holistic approach you guys have as strong as ever? Frank? I think it's stronger. Let me tell you why. There's a massive difference. It's kind of like the Grand Canyon difference between a company showing up with a SerDes and saying, Hey, I have a SerDes, and here's a demo. Than being able to put 200, 500 of those SerDes and make sure they are reliable and they work and they pass all the tests and all the little tricks and all the problems that we have found over the past 20 years, right? In that area, we see that our strength is even growing. Thank you for that. Another question. It looked like on one of your slides you said you have over 200 designs, but the reality, it seems like there's nearly the entire delta from 2016 to 2021 was the TPU. Is that a fair conclusion that the TPU was really the big addition over the last five years? And if that is the case, what's the next inflection point we should be looking at for your ASIC business, in its entirety? Go ahead. Go ahead. When we talk about 200, right? We're talking about 200 tape-outs in the company. That's a variety of chips that are ASICs as well as chips that my colleagues in the standard products are doing, right? In terms of TPUs are large, so they naturally create revenue. In terms of what's gonna come next, as you can probably imagine, we are very respectful of our customers. We're working on areas with our customers that we currently cannot disclose. We remain loyal to them to keep the things that they're doing secret. There's many design wins that we have. Vijay showed, right? The number of TPUs that we have in production this year. We have an even larger number of AI type chips in design. We believe that area continues to be very hot. Another question I got was, Broadcom approached the switching and routing area by doing both merchant and custom silicon over the years, and the merchant approach clearly saw more scale than the custom approach. Why did you choose not to build your own merchant roadmap for the AI side of things and instead focus on the custom silicon? Has that strategy played out as you expected when you compare it to your AI custom sales versus, say, NVIDIA, who's doing more of a general purpose approach for the AI side? Ross, back to our business model. We stick to our knitting, so the expression goes. We have 22 various product franchises, and we invest and run those franchises to keep them sustainable and be leaders in each of these franchises. That's the key of our business model. We do not look at adjacencies and say, Oh, we can do that too, and why not we do it? It takes more than just saying, I can do it technically. It needs an entire business model that is geared, that's focused on winning. One way to say it is all our product lines are very focused in the areas they are in. Just to mention, GPU is not an area we're focused on. It's not one of our product franchises, and so we stay away from it. You're on mute, Ross. Sorry, I clicked myself onto mute instead of off. Another question I had was we understand that Broadcom's ASIC product division includes compute offload, networking, storage, and other custom programs. Additionally, you have custom analog ASICs with some of your other customers. How big is all of the ASIC business as a percentage of your semiconductor revenues? Was that captured by the slide that had, you know, $2-$2.5 billion, or are there other things that you would describe as ASICs as well? It doesn't. The $2.5 billion you showed there that Frank put up did not capture the generic term of what you call an ASIC. This is the difference. Frank runs a business that is very focused, as you say, based on methodology, based on a mix business model of just doing ASIC silicon for very selected customers. It crosses switching and routing, as indicated there, and it crosses now compute offload, of which AI is a big area. It also crosses storage, which we do not highlight because we don't want to, and this is the answer to what you're asking because simply because in, especially in storage, especially in the areas of hard disk drives, the SoCs to two customers, only two customers are pretty much ASICs. We already mentioned it when we talked server storage. We don't want to confuse our investors by double-counting. It's not in there. In fact, figure, just like you correctly pointed out, a lot of the products we do for Apple are ASICs, unique for Apple, and it's done in a separate group outside Frank's. It is a customized chip, you might consider that a customized chip, customized roadmap that Broadcom does for this large customer, and it's not included there. What we include in Frank's area particularly is the focus area of a proven methodology, common IP, common process, and that drives a set business model that Frank and Vijay does. That's what we call custom ASIC. It's certainly more than $2.5 billion. If you talk generically of all ASIC silicon we do in this company. Great, thanks for that answer, Hock. As far as end markets go, obviously we spent a lot of time on compute offload. With Vijay, we talked a bunch about 5G with the case studies that you gave, even some of the optical interconnect side of things with the PAM4. Are there other markets that you think are ripe for ASICs to address? Things like autonomous driving come to mind. But I'm sure there's a wide array of markets that could possibly attract your interest. Do you expect other markets to also be addressed with your ASIC capabilities? If so, what are they? Well, Frank, you want to take that? I can. Yeah. Again, as I mentioned in the presentation, right? We are awake, and we're very agile, so we're paying attention. We don't make the mistake of going into a market way too early when it's very speculative, when we cannot tell who's gonna be the winner, who's gonna be the company that's gonna be leading that pack. There are other markets that we're observing and that we have in some engagements, but we are not gonna talk about them today. Maybe I'll try a different way. Five years down the road, do you think that the business is more or less diversified? I know, Hock, concentration is not something you fear, but by end market, not necessarily by customers, do you think the ASIC business is about the same concentration or more broadly spread? Ross, to be honest, I don't know the answer. Maybe Frank and Vijay have their own views. We don't really know the answer. We do highlight one area which Vijay highlighted, and you mentioned we should deserve some mention, which is the radio, especially in Massive MIMO, the next generation Massive MIMO 5G. You know, RAN, radio access networks, has always been driven very much as ASICs as ASIC silicon. Hasn't changed for 20, 30 years. We, much as people like to talk about O-RAN and stuff like that, we don't see that happening for the next 5 or 10 years. It might be, as Vijay highlighted, a new leg or avenues to revenue stream that we may capture in our ASIC business model. As they adopt the next generation 5G Massive MIMO and they start to deploy less base stations, but much more high-capacity complex base stations. The architecture Vijay put out there of direct RF conversion, full integration of the front end to reduce space, power, because that's a big constraint on deploying base stations, well, might actually take off very fast. It'll be as an ASIC. I doubt it will be a standard product. Was the non-compete that you guys had after you sold the Axxia business something that precluded you from playing in that 5G side or the telecom side in a more general sense for a number of years? I assume, I believe that's no longer an issue as of even a couple of years ago. That's no longer an issue. Got it. One question on a slide, I think it was slide 14, Frank, that you put up that talked about the number of design wins or engagements per node. I think I know the answer to the question, but I've gotten it a couple of times from investors, so I'll ask it anyway. It looked like a decreasing number of engagements or design wins per node. I assume that's just because the time to design wins, and as the node comes closer to reality, more design wins will occur. Is that the reason why? Why are there more or fewer design wins as you go to smaller and smaller nodes? Yeah, that's a very, very good question. Ross, you had it right. There's 2 reasons, right? One of them is, you know, we've been working on 7 nm for a long time, so we accumulated a lot of design wins, and we're gonna get probably an equal number in 5 nm eventually. However, there is a trend that some customers are doing fewer ASICs, but larger ASICs with higher volume. There is a potential that there could be fewer tape-outs, but with higher volume, which actually is not bad. It's actually a really good thing. We are not really seeing that we're not predicting we're gonna have fewer ASICs in 5 nm compared to 7, let's say. However, If a customer wants to do a 7 nm ASIC, we have the flow ready, we can work on it. If they wanna do it in 5 and 3 or 7, we're very open, we're very flexible on that. Great. Thanks for that. A couple shorter term questions, but just to clarify in specific to your guys' businesses. I know substrate shortages, China shutdowns, all those sorts of things, Hock. It might be best answered at a higher level. These aren't necessarily anything new. We've been dealing with it as an industry for a couple of years now, unfortunately. Is there anything specific to the business we're talking about today that either has been or you're worried about being impacted from substrate shortages, shutdowns, those sorts of things? No. Nothing has changed by any material extent at all. Nothing. It doesn't impact. That hasn't impacted the rest of our business and the semiconductor space. Great. I guess another one for Vijay that I got is the telecom operators. Obviously, you have a very impressive list of 5G wins that you're gonna be ramping. You showed those to us. At a high level, those telecom equipment companies have kind of gone between pure ASICs all internally done to some sort of blend of using external folks like yourselves and even doing a little bit more merchant. Do you see them? How do you see that evolving in their internal development versus using companies like Broadcom going forward? Is that really what has changed over the last five years? Is them embracing a kind of a pseudo merchant version of it versus doing everything themselves? Vijay? Yeah. Good question on 5G, right? There is a distinction between radio side of the house and the base station side of the house, right? On the radio side, it has always been custom. It has never gone into any standard silicon. A lot of these algorithms and implementations are something that the OEMs were driving. For the past that I can remember, which is probably 10, 15 years, it's always been a custom play. What we are really doing here is enhancing that custom play with integration of functions that are adjacent, right? I think we talked about the converter integration. When you go more into the base station side of the house, you know, these are referred to as layer one or layer two type ASICs or products. Layer one has stayed predominantly custom or semi-custom. In some cases, I think layer two was, you know, or is today maybe more merchant, but we really don't play there. That's not where our custom business is. Our custom business is predominantly on the radio side. That has always stayed radio, and we see that staying, you know, on custom. If I could enhance that a bit, Vijay. Ross said. What Vijay is also saying, and again, at the risk of overemphasizing, we're coming out as a custom SoC for the digital front end and an analog front end in a manner that has never been done before. That needs to be done. Vijay said that, once you get to 64-channel TRX Massive MIMO, it's physically not possible to deploy those kind of radios, not without the level of integration technology that Vijay outlined there. There isn't. It's too much power, not enough space, and for 64 TX channel or higher. That's the next generation. The only way to do that, because these are distributed physical devices built in onto base stations for 5G, is the architecture we are offering. The reason we are deciding to go big into this space now by investing and what Vijay is outlining is because we see a path where our technology, our design can differentiate itself so dramatically. Otherwise, we don't want to do a me-too product. Great. Well, Hock, I think we've officially exhausted all of the questions from the audience. Thank you for everybody sending them over. We're rapidly approaching the bottom of the hour where we're gonna wrap up anyway. Hock, unless you had any wrap up comments, I just wanted to thank you all for your time and for the great slideshow. I believe the video replay of this will be on the Broadcom website soon enough after this. For those of you that want the slides and the video, et cetera, you'll be able to access it there. Hock, Vijay, and Frank, thank you very much for your time. Thank you. Thank you, everyone. Thank you. Thanks, everybody.