Good day and welcome to the iAccess Alpha Virtual Best Ideas Spring Investment Conference 2026. Our next presenting company is GSI Technology, Inc. If you would like to ask a question during the webcast, you may do so at any point during the presentation by clicking the Ask Question button on the left side of your screen, type your question into the box, and click Send. I'd now like to turn the floor over to today's host, Mr. Didier Lasserre, Vice President of Sales, and Investor Relations for GSI Technology, Inc. Sir, please go ahead. Thank you. Thank you for joining us. As the moderator mentioned, my name is Didier Lasserre. I'm Vice President of Sales and Investor Relations here at GSI. GSI has been a semiconductor company for over 30 years, known for our high-performance SRAM products that are used in networking, defense, and other demanding applications. That business remains an important financial foundation for GSI, being it generates revenue, and cash that support the development of our next-generation technology, the Associative Processing Unit. We are excited about our APU due to our proprietary compute, and memory architecture. Our current product, the Gemini-II, is designed for power and low latency-constrained edge environments such as drones, satellites, and any other autonomous systems, where minimizing data movements enables significantly higher performance per watt than traditional architectures. Gemini-II is already being evaluated in defense, and other edge applications as we work towards initial design wins. Today, I'll briefly walk through the technology behind the compute, and memory architecture, the edge AI market opportunities we're targeting, and how we plan to bring the APU platform into commercial deployments in the upcoming years. The key takeaway I want to leave you with is that edge AI favors architectures that deliver the most compute per watt, and that's exactly what the APU compute, and memory is designed for. I will be making some forward-looking statements, so we have included the safe harbor statement here. A quick overview. As we mentioned, we are a leader in the high-density, high-performance memory market. We've been partnered with TSMC for our wafer fabs for over 30 years, and this will be the same partnership that we'll be using for the APU as well. We've developed, and invented the APU chip, which is, as I mentioned, a compute in memory, a CIM technology. We are targeting the edge. We are not looking at the data centers at the moment, and so the APU is really manufactured, and designed for edge applications. To date, we spent over $175 million on the APU R&D, which has been funded using our SRAM product line. This past October, we raised net $47 million through an equity raise. If you look at our trailing twelve-month revenues, we're just under $25 million. In fact, this month, at the end of this month, we'll finish our fiscal 2026. If you compare what we're running at for this year versus last quarter or, I'm sorry, last year, fiscal 2025, it'll be about a 25% increase in revenue. We outsource the labor-intensive portions of our business, the fab, assembly, you know, day-to-day sales, and so we're able to keep our headcount down to a very efficient 122 employees. The majority of the employees are either hardware or software engineers. We have a very unique architecture, which I'll be talking about extensively today, and we wanna protect that. We've been aggressive with filing patents. We now have 87 patents specifically for the APU. Our balance sheet is strong. We have just over $70 million in cash and cash equivalents. Market cap over $300 million. I want to say this morning we're about $320 million in market cap. A high insider ownership of 20%. Just looking at a high level, you know, what are really the challenges in the AI market space? You know, what's the bottleneck? Really, the bottleneck is the fact that data needs to be moved and transferred constantly within the system. When you're moving data from memory to where the compute elements are, it takes time, it takes latency, and it also takes a lot of power. For edge environments, which is what we're focused on, really the compute is constrained because you have a very limited power budget. This is where the APU fits in perfect because we do, you know, the compute or the processing where the data resides, and I'll explain how that works. If you look on the right, that's essentially what a GPU or CPU looks like. You can see that you have, you know, the DRAM, which is the memory, which is where all the data is stored. If for some reason a GPU needs to do a compute, it needs to grab the data from DRAM, has to transition or be transferred through L2 cache to L1 cache before it gets to the compute elements. Once that data is used in the compute elements, it has to be written back all the way through the same cycle, back through L1, through L2, back to memory. This constant transfer of data, besides taking time, takes a tremendous amount of power. If you look on the left, that's our architecture. Very simple. We actually do the compute or the processing in the memory array itself. The compute bits or the compute elements, processor bits, are physically in the memory array. The memory or the processing is actually where the data resides. We're not having to go fetch it, and then we don't have to write it back. Once we're through using it remains in place. This really significantly increases the performance and lowers the power. Also in our architecture, we have over 1 million bit processors that can work simultaneously. We have massive parallel processing with our technology. Lastly, our resolution or our bit width is not predetermined like GPUs. It's not predetermined to be a 8-bit or a 16-bit. We're a bit engine, and you can configure it any way you want, and it can change from cycle to cycle. If this cycle you want to do some processing at 8-bit, that's fine. Next cycle, let's say you have a model that's most efficient at 3-bit, you can go ahead at 3-bit, no problem. What's interesting is a lot of the AI workloads are moving to the edge, for several reasons. Mainly, what you're finding is that, you know, it's real-time responses are required, and you need to start doing the processing where the data is collected. You know, that transition is happening. Now, the other reasons for that transition are the fact that, cloud computing, besides becoming expensive, it also takes time, and it's also not private. Some of the military and defense applications where the data is not allowed to leave the device for security reasons. Therefore, there's really a huge demand now at the edge for this real-time inference. Why does AI at the edge require a new architecture? If you look at you know the traditional methods, again, as we talked about, the data is separated from the compute, and so you have to go get the data. Again, this constant transferring of data requires time and power. If you look at you know the GSI APU with the data you know in the memory array where the processing is happening, we're able to again lower the latency and lower the power at the same time. You know, GPUs, they're good for data centers. I mean, they're great for training, and they're very good for large data centers. When you get to the edge, power, the performance per watt is critical, and that's where the APU or really shines. This is a true case POC. In fact, this is the POC that we announced last quarter. This is for a drone perimeter security program. At the time, the drone manufacturer needed specific parameters. They needed the time to first token to be no more than three seconds, and they needed, at the time, a system power to be no more than 50 watts, preferably 30 watts. The, you know, this drone manufacturer went to NVIDIA first, and looked at a Jetson, and the Jetson gave them the time to first token that they required, but it was significantly over 100 W for that performance, and that did not work for this drone power budget. They looked at a Snapdragon from Qualcomm, and they were able to achieve the power requirements, but it took 12 seconds to get the first token out. That's four times slower than they could afford. At that point, they looked at the Gemini 2 from GSI. GSI was able to give them the performance of three seconds on the time to first token, along with the 30 W on the power budget. This was, you know, a critical win for us, and we were chosen as the hardware solution for this program. If you look at the market sizes, a lot of folks are really concentrated on, you know, the data center. Everything's about the data center. If you look at the edge AI market, it's gonna be exploding in the future. Right now, it's estimated to be about $20 billion growing to $120 billion by 2030. If you look at the markets that we want to address, we're about $7 billion right now, and it'll be more than doubling in the next five years. These markets, you know, include drones, SAR satellites, any autonomous systems, smart cities, you know, automated warehouses, anything, you know, in that category. We talked about Plato in the past. Plato is our next generation part. It's going to be designed specifically for LLMs at the edge. And I want to emphasize at the edge. Certainly there are GPUs today that are working on LLMs for the data center. Those require over 1 kilowatt of power consumption. If you look at the Plato is gonna be designed to be around 10 watts, and in a lot of cases less than 10 watts to deliver an LLM. It's really designed, again, for the edge. We started the design this past quarter, and we're anticipating having the design done about a year from now, so we'll be taping out in the first half of 2027. If you look at our strategy on how we wanna monetize the APU family, we're gonna be starting with the Gemini two, and we're starting with applications like drones and smart cities, and anything basically physical AI at the edge. You know, we're doing this through POCs and through some of our government contacts, which I'll talk about how we're doing that. Really, it's the you know these advantages with the CIM architecture for things like time to first token and other surrounding awareness that are really gonna be leveraged for all these different applications. The APU gives you that unique architecture for that low power. We anticipate Plato to kick in sometime in 2028, then we're already having discussions with partners on what the generation after Plato looks like. Some of our successes have come from the mil defense areas. We've been very successful with SBIRs, which are essentially grants from the government. To date, we've been awarded $4.4 million worth of SBIRs. I'll start at the bottom about these SBIRs. We had our first phase I win with the U.S. Army second half of last year for $250,000. We also had a win with both the U.S. Air Force Research Laboratory and the Space Development Agency. Both were worth over $1 million. The Space Development Agency SBIR was extended for another $751,000. The purpose for that extension is SDA wanted to see what our commercial chip looked like on a robust level. We're taking this grant to put our commercial Gemini-II under radiation beam and other, you know, ionization type testing to see what it can do. Another grant which will be coming in is the POC that we discussed with our partner G2 Tech in Israel for a program called Sentinel that is for DoD and another foreign defense agency. This is for a drone camera perimeter security environment. This is something that we'll be together with G2 Tech demoing to these agencies in the summertime. As far as future opportunities for SBIRs, we have a pipeline somewhere between $6-$10 million that we have submitted. We feel especially good about one of the submissions that we've done for the U.S. Army on a phase II. It's for a ruggedized edge node that can be used for a lot of different applications from SAR to object detection to drones. We're hoping to hear back on that one shortly. Then we're also going after other funding sources are a little larger than SBIRs. We're looking at ones like STRATFI and TACFI and other ones like BAA, which will give, you know, tens of millions of dollars of grant money. Of course, we're also looking at partnerships with potential customers to have some other strategic funding as well. As far as the financial overview, the revenues have been growing nicely over the last year and a half or so. You know, we dropped off a little bit last quarter, but we're running over $6 million. Operating expenses have been running about $7 million a quarter. You could see a bump up there in our December quarter. That was with the purchase of the IP required for the Plato design to start. That was just over $3 million worth of IP that we purchased that quarter. As far as the cash and cash equivalents, between the $47 million raise that we did in October and some of the ATM purchases during that quarter, you know, our cash went up significantly to just over $70 million. Just on a quick overview of the legacy product line of the SRAMs, we do have the highest density, highest performance memories in the market space. We are at least one to two generations ahead of our nearest competitor. One good news is all of our competitors have frozen their roadmaps, so we'll continue to enjoy that leadership position for the future. The SigmaRAM, SigmaQuad family have really been driving the gross margins, and the revenue because they account for over 50% of our revenues from those families. We're taking that legacy SRAM, and we're hardening it. We have hardened it. We've made rad-hard and rad-tolerant products. These are for satellites, anywhere from the LEO satellites to the GEO satellites. What's unique about this market is its very high ASPs and gross margins. If you look at the range of ASPs, a lower density rad-tolerant might be a few thousand dollars, and a high density rad-tolerant could be as high as $30,000. And again, with gross margins north of 90%. This is, you know, a market that we've talked about in the past. We've sent out lots of different samples, and prototypes for several programs, and we're just waiting for those to go into production. It's a long design cycle for these markets. In summary, again, this computer memory device we have, this architecture really is unique in the fact that it allows us to really decrease latency, decrease power consumption, makes this a perfect use case for edge applications. Anything from drones to satellites, any autonomous systems, smart cities, anything like that is a perfect market to address. You know, we have proven advantages, you know, these SBIR wins. The Cornell paper that went out, you know, last quarter that showed, you know, compared us to a GPU for a RAG application, and it showed that we were more than 99.5% less power for the same performance. The POC, the drone surveillance POC program I mentioned, you know, that was a bake off between us, Qualcomm, and NVIDIA that we won. You know, certainly proven advantages. We like to refer to ourselves as kind of an AI startup. In a lot of cases, you know, I mean, in a lot of cases, we're really not a semiconductor startup. Remember, we've been in the business for 30 years selling and shipping SRAMs, and during that time, we've shipped over 100 million SRAMs. The manufacturing process we're using for SRAMs will be the same for our APU. I mean, we'll be using the same wafer foundry. We'll be using the same assembly house. We'll be using the same testing. We have a proven model, 30 years experience for when we ramp the APU. Those SRAMs have been funding non-dilutive the APU R&D. We have a strong balance sheet, with, you know, again, over $70 million in cash with no debt. At this point, open it up to questions or Q&A. Okay, so the first question. Given Gemini Two's ultra-low power and low latency performance, where do you see the strongest initial deployment verticals across drones and surveillance? So yeah, certainly drones, we've done a significant amount of software work on SAR object detection and now time to first token. And then again, this POC that we're doing, it's, you know, with the demo going in the summer, it's with the intent to sell these to the DoD and other government agencies. So certainly, that will be the first area. What portion of future revenues do you expect to come from defense versus commercial edge applications over the next two to three years? That's a good question. It's gonna be a little, you know, leaning more towards the defense versus commercial. That's because that's where we've seen our early successes. Between the interest from the DoD SBIRs that we've won, along with this POC, we certainly see that that's gonna be the first, you know, entry into revenue. Again, we're trying to follow that up quickly with other applications like smart cities. For the next two to three years, it'll be leaning much more towards the defense side. Let me see here. What is the size of the Gemini-II cache? Right now it's 96 MB of memory on the Gemini Two. That's eight times more than Gemini-I. Candidly, on the Plato it will be less, the internal cache. As you recall, with Plato it's gonna be a different application. It's gonna be LLMs. LLMs, by definition, large language models, won't fit inside of a chip. What we've done is we've actually lowered the cache on that one in order to be able to really increase the pipeline, the bandwidth to be able to get extra data in the chip. 96 MB for Gemini Two. Did you publish the details for where the three-second figure for the Jetson Thor came from? That came from the drone manufacturer who did the bake off. The numbers that we presented were the numbers that they did in a benchmark program that they did. I'm sorry. Are you going to move from DDR4 to HBM2 to avoid external memory bottlenecks? No. We're actually gonna be going to GDDR5 for Plato. Again, these are edge applications, and so we need to keep them low power and lower cost as well. It's prohibitive moving to HBM for that. We'll be going with the GDDR5. Comment. Please comment on the ATM. Right now, the ATM is not active. I think there is $2 million that were left on it, but at this point it's not active. Let me see. Okay. Are potential partners already driving decisions making the Plato roadmap? Yes. And again, the current Plato program, as well as, well, we'll call it Plato 2, a future Plato. Yes, those are definitely with partners. Is the 98% power savings reported by Cornell based on simulated HBM external memory interface? Candidly, I don't believe it was simulated. I think that they actually did a program, but the Cornell paper is out there for you to be able to read it, you know, and you know, go through that. But candidly, I don't remember, you know, what the memory interface was. Is manufacturing in Taiwan? Yes. We use, as I mentioned, TSMC as our fab. We use, excuse me, a company called ASE to do our assembly, and we do our own testing. We have a facility in Sunnyvale, California, which we do all the R&D testing, and then when it goes into mass production, it goes to our Taiwan facility, excuse me, for the testing. You received a reported three-second time to first token for Gemma 3 12B on Gemini-II. Can you confirm that the benchmark was achieved on the final product silicon? And are there plans to release a live demo for third-party audit? Yes, the three-second time to first token was done on the current silicon, which is gonna be our production silicon. And, as I mentioned, the demo right now is going to be done sometime in the summer is when it's scheduled to be. Let me see here. Do you expect to raise more money anytime soon, and are you looking, are you talking to any strategic investors? Also, is the SRAM business potentially up for sale? You know, we're certainly, you know, to scale, we're not actively looking to raise more money, but more money will be needed, I'm sure, in the future. Is the SRAM business potentially up for sale? Well, that's a good question. Certainly, if the right opportunity came, you know, we would certainly, you know, entertain that. At this point I am actually out of time. Operator? Thank you, sir. Ladies and gentlemen, that concludes GSI Technology, Inc.'s presentation. You may now disconnect and please consult the conference agenda for the next presenting company.