Slides
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Ashish Saran SVP , Investor Relations
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© 2025 Marvell. All rights reserved. 3 Forward-looking statements Except for statements of historical fact, this presentation contains forward-looking statements (within the meaning of the federal securities laws) including, but not limited to, statements related to market trends and to the company’s business and operations, business opportunities, growth strategy and expectations, and financial targets and plans, that involve risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “plans,” “projects,” “believes,” “seeks,” “estimates,” “can,” “may,” “will,” “would” and similar expressions identify such forward-looking statements. These statements are not guarantees of results and should not be considered as an indication of future activity or future performance. Actual events or results may differ materially from those described in this presentation due to a number of risks and uncertainties. For factors that could cause Marvell’s results to vary from expectations, please see the risk factors identified in Marvell’s Quarterly Report on Form 10-Q for the fiscal quarter ended May 3, 2025, as filed with the SEC on May 30, 2025, and Marvell’s Annual Report on Form 10-K for the fiscal year ended February 1, 2025, as filed with the SEC on March 12, 2025, and other factors detailed from time to time in Marvell’s filings with the SEC. The forward‐looking statements in this presentation speak only as of the date of this presentation and Marvell undertakes no obligation to revise or update publicly any forward-looking statements.
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© 2025 Marvell. All rights reserved. 4 Non-GAAP financial measures ▪ During this presentation, we may refer to certain financial measures on a U.S. non-GAAP basis. ▪ We believe that the presentation of non-GAAP financial measures provides important supplemental information to management and investors regarding financial and business trends relating to our financial condition and results of operations. ▪ While we use non-GAAP financial measures as a tool to enhance our understanding of certain aspects of our financial performance, we do not consider these measures to be a substitute for, or superior to, the information provided by GAAP financial measures. ▪ A reconciliation in accordance with SEC Regulation G for non-GAAP financial measures is available in the Investor Relations section of our website at https://www.marvell.com.
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© 2025 Marvell. All rights reserved. 5 Matt Murphy Chairman and Chief Executive Officer Chris Koopmans Chief Operating Officer Q&A Nick Kucharewski SVP and GM, Cloud Platform Sandeep Bharathi Chief Development Officer Will Chu SVP and GM, Custom Cloud Solutions Agenda
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© 2025 Marvell. All rights reserved. 6
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Matt Murphy Chairman and Chief Executive Officer
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© 2025 Marvell. All rights reserved. 8 Cloud-optimized silicon © 2021 Marvell. All rights reserved. 8
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© 2025 Marvell. All rights reserved. 9
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© 2025 Marvell. All rights reserved. 10 AI infrastructure buildout drives incredible growth 46% CAGR Top 4 U.S. hyperscaler CAPEX Source: public information $153B $248B $327B CY23 CY24 CY25
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© 2025 Marvell. All rights reserved. 11 Emerging hyperscalers rising fast © 2025 Marvell. All rights reserved. 11 Models • • • Sovereign AI Applications STARGATE • • • • • •
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© 2025 Marvell. All rights reserved. 12 AI infrastructure buildout drives incredible growth 46% CAGR Top 4 U.S. hyperscaler CAPEX Source: public information $153B $248B $327B CY23 CY24 CY25
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© 2025 Marvell. All rights reserved. 13 AI infrastructure buildout drives incredible growth 51% CAGR Total data center CAPEX Source: public information, Dell’Oro $260B $435B $593B CY23 CY24 CY25 S T A R G A T E
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© 2025 Marvell. All rights reserved. 14 To reach $1 trillion by 2028 20% CAGR Source: public information, Dell’Oro $260B $435B $593B CY23 CY24 CY25 S T A R G A T E $1,022B CY28
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© 2025 Marvell. All rights reserved. 15 Storage 7% CAGR Interconnect 27% CAGR Switching 15% CAGR Accelerated custom compute 45% CAGR $21B $6.6 $4.2 $6.1 $4.3 CY23 $75B $5.9 $13.9 $12.0 $42.9 CY28 Marvell ® data center TAM 29% CAGR Data center TAM: AI Day April 2024 Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates
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© 2025 Marvell. All rights reserved. 16 $94B $6.5 $19.0 $13.2 $55.4 CY28 update $21B $6.6 $4.2 $6.1 $4.3 CY23 $75B $5.9 $13.9 $12.0 $42.9 CY28 prior Marvell data center TAM Storage 9% CAGR Interconnect 35% CAGR Switching 17% CAGR Accelerated custom compute 53% CAGR +26% larger Compute is 29% larger, interconnect is 37% larger Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates
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© 2025 Marvell. All rights reserved. 17 $94B $6.5 $19.0 $13.2 $55.4 CY28 Storage 9% CAGR Interconnect 35% CAGR Switching 17% CAGR Accelerated custom compute 53% CAGR $21B $6.6 $4.2 $6.1 $4.3 CY23 Marvell data center TAM 35% CAGR Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates
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© 2025 Marvell. All rights reserved. 18 Accelerated custom compute 53% CAGR $94B $6.5 $19.0 $13.2 $55.4 CY28 $21B $6.6 $4.2 $6.1 $4.3 CY23 Marvell data center TAM Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates
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© 2025 Marvell. All rights reserved. 19 Expanding opportunity with custom XPU attach Accelerated custom compute TAM = XPU Custom XPU XPUs
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© 2025 Marvell. All rights reserved. 20 Expanding opportunity with custom XPU attach Accelerated custom compute TAM = XPU + XPU attach Memory Networking Networking Co-processor Scale-up fabric Custom XPU attach Network interfaces, scale-up fabrics, security and host management co-processors, memory poolers and expanders, etc. Custom XPU XPUs
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© 2025 Marvell. All rights reserved. 21 XPU attach becoming increasing portion of custom TAM $55.4B $40.8 $14.6 CY28 $6.6B $6.0 $0.6 CY23 Custom XPU 47% CAGR Custom XPU attach 90% CAGR 53% CAGR Source: 650 Group, Dell’Oro, and Marvell estimates
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© 2025 Marvell. All rights reserved. 22 Accelerated custom compute sockets Top 4 U.S. hyperscalers Custom XPU sockets 3 Custom XPU attach sockets 9 Expanding multi-generational relationships Emerging hyperscalers Custom XPU sockets 2 Custom XPU attach sockets 4 1812 6
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© 2025 Marvell. All rights reserved. 23 Custom opportunity explosion PIPELINE Opportunities 1/3 custom XPU 2/3 custom XPU attach Each XPU Multi-$B lifetime 18 - 24 months Each XPU attach Several-$100M lifetime 2 - 4 years Opportunities >50 Customers >10 Lifetime revenue $75B
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© 2025 Marvell. All rights reserved. 24 Why we win: differentiating with full-service custom Manufacturing and logistics PackagingSilicon services Design IPSystem architecture
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© 2025 Marvell. All rights reserved. 25 Leading-edge technology drives multi-gen wins Process IP Packaging World’s first 448G electrical and optical SerDes Advanced packaging Nanometers to angstroms OFC 2025 demo 2nm 16Å 14Å
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© 2025 Marvell. All rights reserved. 26 EDA in the cloud Custom and networking silicon © 2025 Marvell. All rights reserved. 26
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© 2025 Marvell. All rights reserved. 27 EDA in the cloud Custom and networking silicon © 2025 Marvell. All rights reserved. 27 “ ” Building a cost and power efficient cloud at the scale that only AWS can deliver begins with leading-edge semiconductors designed to meet the demanding infrastructure needs of our customers. Our expanded collaboration with Marvell enables us to deploy our comprehensive semiconductor portfolio and specialized networking hardware to advance our mission to provide the industry’s most robust and scalable cloud and AI services to our customers. Matt Garman, CEO at AWS
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© 2025 Marvell. All rights reserved. 28 Rani Borkar Corporate Vice President, Azure Hardware Systems and Infrastructure, Microsoft Video content
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© 2025 Marvell. All rights reserved. 29 Marvell’s data center revenue ~$0.5B ~$3.7B FY25 Cloud AI On-prem $4.2B Future >50% custom Q4 FY25 >25% custom
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© 2025 Marvell. All rights reserved. 30 Driving to 20% share in custom compute and attach $55.4B $40.8 $14.6 CY28 Market share target 20% Market share <5% $6.6B $6.0 $0.6 CY23 Custom XPU 47% CAGR Custom XPU attach 90% CAGR 53% CAGR Source: 650 Group, Dell’Oro, and Marvell estimates
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© 2025 Marvell. All rights reserved. 31 On track for 20% share in overall data center $94B $6.5 $19.0 $13.2 $55.4 CY28 $40.8 $14.6 $13.2 $19.0 $6.5 CY23 $21B $6.0 $4.2 $6.1 $4.3 $0.6 Storage 9% CAGR Interconnect 35% CAGR Switching 17% CAGR Custom XPU 47% CAGR Custom XPU attach 90% CAGR Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates
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© 2025 Marvell. All rights reserved. 32 On track for 20% share in overall data center $94B $6.5 $19.0 $13.2 $55.4 CY28 $40.8 $14.6 $13.2 $19.0 $6.5 Market share~10% CY23 $21B Storage 9% CAGR Interconnect 35% CAGR Switching 17% CAGR Custom XPU 47% CAGR Custom XPU attach 90% CAGR Market share target 20% $33B CY24 ~13% Market share based on Marvell fiscal year Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates
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© 2025 Marvell. All rights reserved. 33 © 2025 Marvell. All rights reserved. 33 $75B >50 opportunities Larger TAM $75B $94B Increasing share ~10% ~13% ... 20% More sockets won 3 18 More customers 4 >10 New markets Custom XPU Custom XPU attach
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© 2025 Marvell. All rights reserved. 34
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Chris Koopmans Chief Operating Officer
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© 2025 Marvell. All rights reserved. 36 CY28 $1,022BData center CAPEX to reach $1 trillion by 2028 CY23 CY24 CY25 Source: Company public information, Dell’Oro $593B $260B $435B 20% CAGR S T A R G A T E
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© 2025 Marvell. All rights reserved. 37 Semiconductor TAM $494B 2028 data center infrastructure market Equipment CAPEX (excluding physical infrastructure) $825B Source: 650 Group, CignalAI, Dell’Oro, LightCounting, and Marvell estimates Data center CAPEX $1,022B Accelerated compute TAM $349B
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© 2025 Marvell. All rights reserved. 38 XPU HBM attach XPU attach Breaking down accelerated computing TAM Accelerated compute $349B $163 $58 $128 $349B CY28 $172B CY28 updateCY28 prior >2X Source: 650 Group, Dell’Oro, and Marvell estimates
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© 2025 Marvell. All rights reserved. 39 Breaking down accelerated computing TAM Accelerated compute $349B $163 $58 CY28 $172B >2X CY28 updateCY28 prior $221B HBM attach XPU HBM attach XPU attach Source: 650 Group, Dell’Oro, and Marvell estimates
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© 2025 Marvell. All rights reserved. 40 Custom silicon on track for 25% share of market by 2028 Accelerated compute $163 $58 XPU XPU attach $221B $14.6 $40.8 $55.4B CY28 Custom XPU Custom XPU attach 25% Custom accelerated compute CY28 update Source: 650 Group, Dell’Oro, and Marvell estimates
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© 2025 Marvell. All rights reserved. 41 Marvell custom silicon TAM $14.6 $40.8 $55.4B CY28 Custom XPU 47% CAGR Custom XPU attach 90% CAGR Marvell TAM $6.6B CY23 $6.0 $0.6 53% CAGR Source: 650 Group, Dell’Oro, and Marvell estimates
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© 2025 Marvell. All rights reserved. 42 Diversity drives specialization, which drives customization © 2025 Marvell. All rights reserved. 42 Why custom?
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© 2025 Marvell. All rights reserved. 43 Race to the million-XPU cluster speeding up © 2025 Marvell. All rights reserved. 1M XPUs 200K XPUs 2025 xAI 100K XPUs 2024 Meta 14K XPUs 2023 Microsoft 10K XPUs 2020 Microsoft 43
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© 2025 Marvell. All rights reserved. 44 Large language model Content writing Live chatbots Search Analyze Conclude Code writing Complex math Puzzle solving Reasoning model 44© 2025 Marvell. All rights reserved. Model innovation continues Rise of inference-optimized infrastructure
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© 2025 Marvell. All rights reserved. 45 One size does not fit all As AI workloads diversify, so must the infrastructure Training InferenceChain of thought inference 45© 2025 Marvell. All rights reserved.
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© 2025 Marvell. All rights reserved. 46 Diversification creates more opportunities
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© 2025 Marvell. All rights reserved. 47 Specialization drives diversity of compute core design Programmable, powerful, purpose-built Inside the XPU Multiple points of optimization Core architectures # cores Level of precision Ratio of cores to memory Compute cores On-chip SRAM Interfaces
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© 2025 Marvell. All rights reserved. 48 And diversity of memory, packaging, connectivity Beyond one chip, advanced packaging powers scale XPU HBM HBM HBM HBM HBM HBM XPU HBM HBM HBM HBM HBM HBM Interfaces Interfaces
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© 2025 Marvell. All rights reserved. 49 And diversity of the entire scaled -up platform design Optimized infrastructure for specific workloads Dual AI rack
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© 2025 Marvell. All rights reserved. 50 AI infrastructure platform options General-purpose platform Custom Custom Full-custom platform Third-party platform Custom Standards- based platform Custom NVLink Fusion announced May 18 UALink announced June 11 XPU XPU attach
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© 2025 Marvell. All rights reserved. 51 AI infrastructure platform options General-purpose platform Custom Custom Full-custom platform Third-party platform Custom Standards- based platform Custom NVLink Fusion announced May 18 UALink announced June 11 XPU XPU attach Increasing custom XPU attach
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© 2025 Marvell. All rights reserved. 52 Custom XPU 47% CAGR Custom XPU attach 90% CAGR Growing TAM supports further pipeline expansion $14.6 $40.8 CY28 $55.4B 18 current sockets targeting 20% share >50 opportunities driving $75B Source: 650 Group, Dell’Oro, and Marvell estimates
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© 2025 Marvell. All rights reserved. 53
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Nick Kucharewski SVP and GM, Cloud Platform
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© 2025 Marvell. All rights reserved. 55 Marvell Custom Cloud Solutions 30 years of experience First-time-right silicon design Comprehensive portfolio Silicon-proven core enabling IP Full-lifecycle partnership Definition through deployment © 2025 Marvell. All rights reserved. 55
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© 2025 Marvell. All rights reserved. 56 Choosing a custom silicon partner © 2025 Marvell. All rights reserved. 56
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© 2025 Marvell. All rights reserved. 57 Pace of innovation in AI cloud infrastructure … applications demand system innovation every < 2 years … a 1-day delay means millions $ in lost revenue New key enabling technologies every year © 2025 Marvell. All rights reserved. 57
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© 2025 Marvell. All rights reserved. 58 © 2025 Marvell. All rights reserved. 58 Manufacturing Manufacturi ng and l ogistics Physical design services Manufacturi ng and l ogistics Si licon services Full-service custom Manufacturing and logistics Silicon services PackagingDesign IPSystem architecture
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© 2025 Marvell. All rights reserved. 59 Marvell: Full-Lifecycle Custom Cloud © 2025 Marvell. All rights reserved. 59 Unique differentiated technology, not available on the open market Manufacturing and logistics PackagingSilicon services Design IPSystem architecture
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© 2025 Marvell. All rights reserved. 60 © 2025 Marvell. All rights reserved. 60 New technology development Incubation 2-4 years before project start Evaluation and assessment Concept systems enable customer exploration Cooperative system definition Iterate on power, performance, cost tradeoffs Projects begin years ahead of time System architecture
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© 2025 Marvell. All rights reserved. 61 © 2025 Marvell. All rights reserved. Marvell Design IP Key enabling core tech Start-ups Ecosystem Compute cores Packet processing Compute fabric SerDes Die-to-die Custom HBM Dense SRAM Hardened Arm Optics Compress / decompress Ethernet MAC Packet fabric Specialized SW/FW SecurityMulti-die
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© 2025 Marvell. All rights reserved. 62 © 2025 Marvell. All rights reserved. 16/14Å2nm3nm5nm 62 Test silicon IP migration EDA toolflow Model creation Running ahead of the customer project Process enablement Logic design Physical design DFT and DFM Power tuning Yield enhancement Design execution Silicon services
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© 2025 Marvell. All rights reserved. 63 © 2025 Marvell. All rights reserved. Marvell custom and TSMC CoWoS Marvell custom and JEDEC CPO Co-packaged optics CPC Co-packaged copper The key to scaling beyond Moore’s Law Packaging Leadership roadmap Multi-die HBM Advanced substrate
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© 2025 Marvell. All rights reserved. 64 © 2025 Marvell. All rights reserved. 64 Scale Leading fabless manufacturer Quality Billions of device-hours over multiple decades Readiness Operations engineering for volume delivery Test engineering Product engineering Quality assurance Reliability assessment Delivering quality at massive scale Manufacturing and logistics
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© 2025 Marvell. All rights reserved. 65 © 2025 Marvell. All rights reserved. 65 Manufacturing Manufacturi ng and l ogistics Physical design services Manufacturi ng and l ogistics Si licon services Full-service custom Manufacturing and logistics Silicon services PackagingDesign IPSystem architecture
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© 2025 Marvell. All rights reserved. 66 10x every ~2 years Running faster and faster © 2025 Marvell. All rights reserved. 66 Leading systems need access to the leading tech, every generation Process technology 3nm, 2nm, 16/14Å… Advanced packaging 2.5D, 3.5D, advanced… Networking protocols Ethernet, NVLink, UALink… ~2x every ~2 years High-speed SerDes 224 Gbps, 448 Gbps… Die-to-die interconnect 16 Gbps, 32 Gbps, 64 Gbps…
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© 2025 Marvell. All rights reserved. 67 © 2025 Marvell. All rights reserved. 67 Fabric CPU Accelerator Interconnect NIC Switch Partnership for system design Exclusive enabling technology Experience at volume scale Marvell Full-Lifecycle Custom Cloud
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© 2025 Marvell. All rights reserved. 68
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Sandeep Bharathi Chief Development Officer
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Mark Kuemerle VP , Technology, Custom Cloud Solutions Radha Nagarajan SVP and CTO, Optical Engineering Ken Chang SVP, Analog and Mixed Signal Engineering Mayank Mayukh Senior Distinguished Engineer, Advanced Packaging
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© 2025 Marvell. All rights reserved. 71 AI compute cycle accelerates General - purpose compute AI compute doubling less than a year 2 years < 1 year Accelerated infrastructure
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© 2025 Marvell. All rights reserved. 72 Source: Adapted from TSMC slide from IEDM conference. Mass production 2020 20302000 >10M >1B 10B 20-50B >100B >200B 3D and multi-die integration >500B >1T 200B AI accelerates single-die to multi-die transition Monolithic integration Transistors
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© 2025 Marvell. All rights reserved. 73 Source: Adapted from TSMC slide from IEDM conference. 2020 20302000 >10M >1B 10B 20-50B >100B >200B >500B >1T 200B Trillion+ transistors requires rack-scale integration AI accelerates single-die to multi-die transition Transistors
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© 2025 Marvell. All rights reserved. 74 © 2025 Marvell. All rights reserved. 74 Proven Marvell technology stack Process IP Package Design flow Multi-generational execution track record
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© 2025 Marvell. All rights reserved. 75 © 2025 Marvell. All rights reserved. Process IP Package Design flow 75
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© 2025 Marvell. All rights reserved. 76 N3P N2P A14 A16 N5P Most advanced process nodes Process technology leadership Foundry process enabled Test chip IP Product development start Product shipped 3-4 years lead time Validated critical IP aheadof product development 76
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© 2025 Marvell. All rights reserved. 77 Marvell IP across process technologies CMOS Silicon germanium Silicon photonics Foundries Process-agnostic. Foundry-ready. Future-proof.
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© 2025 Marvell. All rights reserved. 78 © 2025 Marvell. All rights reserved. Process IP Package Design flow 78
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© 2025 Marvell. All rights reserved. 79 © 2025 Marvell. All rights reserved. Anatomy of a modern XPU Industry-leading customized IP portfolio SerDes Custom HBM Die-to-die Custom SRAM Silicon photonics D2D D2DD2DD2D D2DD2D D2D SerDes HBM HBM HBM HBM HBM HBM Dense SRAM Dense SRAM CPOCPO CPOCPO D2D SerDes Dense SRAM
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© 2025 Marvell. All rights reserved. 80 © 2025 Marvell. All rights reserved. SerDes Custom HBM Die-to-die Custom SRAM Silicon photonics Anatomy of a modern XPU
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© 2025 Marvell. All rights reserved. 81 © 2025 Marvell. All rights reserved. Advanced packaging SerDes Custom HBM Die-to-die Custom SRAM Silicon photonics Anatomy of a modern XPU
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© 2025 Marvell. All rights reserved. 82 © 2025 Marvell. All rights reserved. Modern XPU and XPU attach D2D SerDes D2D SerDes D2D SerDes D2D SerDes Dense SRAM Dense SRAM D2D SerDes D2D SerDes D2D SerDes D2D SerDes Dense SRAM Dense SRAM D2D SerDes CPOCPO CPOCPO D2D SerDes D2DD2DD2D D2DD2D D2D Dense SRAM Dense SRAM Dense SRAM D2D D2DD2DD2D D2DD2D D2D SerDes HBM HBM HBM HBM HBM HBM Dense SRAM Dense SRAM CPOCPO CPOCPO D2D SerDes Dense SRAM
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© 2025 Marvell. All rights reserved. 83 © 2025 Marvell. All rights reserved. Customization to achieve the highest performance per watt Modern XPU and XPU attach D2D SerDes D2D SerDes D2D SerDes D2D SerDes Dense SRAM Dense SRAM D2D SerDes CPOCPO CPOCPO D2D SerDes D2DD2DD2D D2DD2D D2D Dense SRAM Dense SRAM Dense SRAM
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© 2025 Marvell. All rights reserved. 84 © 2025 Marvell. All rights reserved. 84 Figures of merit Why is SerDes so difficult? Marvell has multi-generational SerDes leadership Reach Power Latency Bit error rate
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© 2025 Marvell. All rights reserved. 85 Marvell IP leadership Focused investment enables first-to-market advantage Co-packaged optics SerDes Custom HBM Die-to-die Custom SRAM Silicon photonics Advanced packaging © 2025 Marvell. All rights reserved. 85
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© 2025 Marvell. All rights reserved. 86
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Ken Chang SVP , Analog and Mixed Signal Engineering
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© 2025 Marvell. All rights reserved. 88 Marvell SerDes leadership in IEEE spotlight Marvell SerDes recognized by IEEE Source: ISSCC, VLSI, OFC, industry SerDes papers 50 400 2018 2020 2022 2024 2026 SerDes line rate vs. year and technology 3nm 4nm 7nm 5nm Key leadership metrics Lowest power Highest reach Lowest BER Lowest area Marvell 100 200 Line rate (Gb/s)
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© 2025 Marvell. All rights reserved. 89 Marvell SerDes leadership in IEEE spotlight ISSCC 2022 ISSCC 2024 VLSI 2024 VLSI 2025ISSCC 2025 OFC 2025 Demo Electrical SerDes Optical SerDes 3nm 224G LR 5nm 224G LR 5nm 112G LR 3nm 128G LR 5nm 112G XSR 3nm 112G XSR 5nm 200G/lane optical retimer 5nm 100G/lane optical retimer 3nm 200G/lane optical retimer 3nm 400G/lane 5nm 100G/lane optical retimer 5nm 200G/lane optical gearbox Enabling next-generation XPU platforms
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© 2025 Marvell. All rights reserved. 90 Marvell 3nm 224Gbps SerDes at OFC Enabling next-generation XPU platforms Level 1 Level 4 Level 3 Level 2 Receiver input: closed eye After receiver / DSP: open levelsTransmitter output: clean eye 2m cable, 50dB loss bump-to-bump
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© 2025 Marvell. All rights reserved. 91 Marvell die-to-die (D2D) Today Tomorrow Future 10-20 Tbps / mm ~ 0.3pJ/bit 30+ Tbps / mm ~ 0.2pJ/bit 50+ Tbps / mm <0.1pJ/bit GL-102 packagePackage Chip ALR Chip B LRD2D D2D Interposer Beachfront
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© 2025 Marvell. All rights reserved. 92
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Mark Kuemerle VP , Technology, Custom Cloud Solutions
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© 2025 Marvell. All rights reserved. 94 Custom dense SRAM On-chip embedded SRAM – customization is key D2D D2DD2DD2D D2DD2D D2D SerDes HBM HBM HBM HBM HBM HBM Dense SRAM Dense SRAM CPOCPO CPOCPO D2D SerDes Dense SRAM
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© 2025 Marvell. All rights reserved. 95 17x Marvell custom SRAM Comparison of 1 Mb instance of third-party dense memories vs. Marvell Marvell IP provides 17x bandwidth-density improvement Marvell vs. industry Area at same bandwidth 50% lower Standby power 66% lower Bandwidth at same area 17x higher Key metrics for embedded memories Bandwidth / mm2 of memory options HBM4E Marvell Best available SRAM Bandwidth / mm 2
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© 2025 Marvell. All rights reserved. 96 Custom HBM – high capacity with minimal overhead Custom HBM D2D D2DD2DD2D D2DD2D D2D SerDes HBM HBM HBM HBM HBM HBM Dense SRAM Dense SRAM CPOCPO CPOCPO D2D SerDes Dense SRAM
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© 2025 Marvell. All rights reserved. 97 Enhancing XPUs with custom HBM architecture ▪ 1X useful compute area ▪ No compute area on HBM ▪ 1X power ▪ 1.7X useful compute area ▪ More compute area on HBM ▪ 75% lower memory I/O power Compute area More area Standard HBM No chiplets Marvell Custom HBM With I/O chiplets Compute area Custom HBM XPUStandard HBM XPU
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© 2025 Marvell. All rights reserved. 98 Package-integrated voltage regulation (PIVR) 60% lower power noise Typical accelerator PIVR on underside Standard practice Marvell PIVR 85% lower IR power 15% lower total product power
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© 2025 Marvell. All rights reserved. 99
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Radha Nagarajan SVP and CTO, Optical Engineering
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© 2025 Marvell. All rights reserved. 101 © 2025 Marvell. All rights reserved. 101 Silicon photonics is critical for co -packaged optics Highly integrated light engines for all interconnects ▪ Optical system-on-chip ▪ High speed, long reach ▪ High volume CMOS fabs ▪ Complex electronics and photonics integration
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© 2025 Marvell. All rights reserved. 102 Marvell silicon photonics at scale Multiple generations of field-deployed silicon photonics 100G Field-proven 2017 400G 2020 Shipping 800G 2023 Sampling 1.6T 2026 Development
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© 2025 Marvell. All rights reserved. 103 450 Gbps Optical demo OFC March 2025 enabled by Marvell high-speed analog components Marvell breaking 500 Gbps data rate barrier Data rate and analog bandwidth (GHz) scaling 224 Gbps 480 Gbps Today 2X analog bandwidth every 2 years 112 Gbps Electrical eye at 480 Gbps Enables Application Single optical lane Lanes Format 1.6T ZR Between DC 1.6T 1 Coherent 12.8T CPO Inside DC 448G 32 PAM4
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© 2025 Marvell. All rights reserved. 104 Marvell high-density custom silicon interconnects for AI 104 Co-packaged optics to custom silicon interconnect 6.4T per engine 32 x 224G optical lanes 25.6T 4 engines Custom silicon interconnect High-density light engines Electronics Photonics Substrate Integration on reverse side 3D integrated silicon photonics light engine
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© 2025 Marvell. All rights reserved. 105
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Mayank Mayukh Senior Distinguished Engineer, Advanced Packaging
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© 2025 Marvell. All rights reserved. 107 Marvell advanced packaging strategy + Proprietary technology Materials, process, design Strategic partnership Foundry, OSATs, substrate, materials Scaling, optics, copper, components Fungible building blocks Generational portfolio Long-range roadmap for building blocks = Custom packaging solution Faster cadence Robust ecosystem for faster cadence between custom packaging generations © 2025 Marvell. All rights reserved. 107
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© 2025 Marvell. All rights reserved. 108 Marvell advanced packaging portfolio 2.5D package Silicon chiplets Interposers 4D package Advanced substrates 4.5D package Integrated optics and copper Stacked silicon chiplets 3.5D package Yesterday Today Tomorrow Road to packaging a trillion transistors together 2D package SubstrateSilicon Lid 8X 16X4X1X © 2025 Marvell. All rights reserved. 108
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© 2025 Marvell. All rights reserved. 109 Marvell advanced packaging toolbox Advanced substrates Bridge or RDL interposer 3D-stacked silicon chiplets Integrated optics and copper Fungible toolbox for generational portfolio
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© 2025 Marvell. All rights reserved. 110
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Will Chu SVP and GM, Custom Cloud Solutions
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+ Custom Cloud Solutions Compute ASIC © 2025 Marvell. All rights reserved. 112
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© 2025 Marvell. All rights reserved. 113 Strong design win momentum Accelerated custom compute sockets Top 4 U.S. hyperscalers Custom XPU sockets 3 Custom XPU attach sockets 9 Emerging hyperscalers Custom XPU sockets 2 Custom XPU attach sockets 4 1812 6
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© 2025 Marvell. All rights reserved. 114 Typical system architecture XPUsMemory Networking Networking Co-processor Scale-up fabric Custom XPU attach Custom XPU
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© 2025 Marvell. All rights reserved. 115 Providing unique customer value: typical XPU © 2025 Marvell. All rights reserved. 115 Rack-scale enablement and optimization System architecture Critical IPs Die-to-dieSerDes Dense SRAM Hardened Arm Design IP Marvell custom and TSMC CoWoS Packaging Design-to-spec and co-development Si licon services Faster time to marketManufacturi ng and l ogistics
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© 2025 Marvell. All rights reserved. 116 Providing unique customer value: typical XPU attach © 2025 Marvell. All rights reserved. 116 Production FW/SW, boards, and ecosystemSystem architecture Critical IPs Compute fabric SerDes Compress / decompress Security Design IP Design-to-spec integrating customer IPSi licon services
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© 2025 Marvell. All rights reserved. 117 Full ownership end-to-end Unique value across a single complete program Invest ahead Co-development Unmatched combination of technology, expertise and scale IP development Execution System architecture Qualification Ship
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© 2025 Marvell. All rights reserved. 118 Qualification IP development (3nm) Execution Ship System architecture Unique value driving multi-generational partnerships Qualification IP development (2nm) Execution Ship System architecture Qualification IP development (16Å) Execution Ship System architecture Concurrent engagement enables a new chip every year
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© 2025 Marvell. All rights reserved. 119 Investing ahead in breakthrough technologies Marvell Demonstrates Industry’s Leading 2nm Silicon for Accelerated Infrastructure March 3, 2025 Marvell Develops Industry’s First 2nm Custom SRAM for Next-Generation AI Infrastructure Silicon June 17, 2025 Marvell Announces Breakthrough Co-Packaged Optics Architecture for Custom AI Accelerators January 6, 2025 Marvell Announces Breakthrough Custom HBM Compute Architecture to Optimize Cloud AI Accelerators December 10, 2024 Marvell Introduces Optimized Integrated Power Solutions to Boost Performance, Efficiency, and ROI of Accelerated Infrastructure June 17, 2025 Marvell Delivers Advanced Packaging Platform for Custom AI Accelerators May 9, 2025
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© 2025 Marvell. All rights reserved. 120 Rapidly expanding pipeline Engaged in every opportunity and well-positioned for growth 1/3 custom XPU 2/3 custom XPU attach Opportunities >50
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