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Micron Confidential Micron Confidential Technology and products leadership for the AI era October 21, 2026
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2 Legal disclaimer This presentation contains forward-looking statements regarding our industry, our strategic position, customer demand, investments and the goals for such investments, our business opportunities, our products and technology, including our product and technology roadmaps and expected capabilities and timing, and our financial and operating performance. These forward-looking statements are subject to a number of risks and uncertainties that could cause actual results to differ materially. For a discussion of these risks and uncertainties, please refer to our filings with the Securities and Exchange Commission. Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance, or achievements. We are under no duty to update any of the forward-looking statements, except as required by applicable law.
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3 Scott DeBoer President and Chief Technology and Products Officer 3
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4 • AI has created unprecedented opportunity for memory and storage; Micron has executed and delivered • Micron’s technology leadership is foundational to delivering differentiated, industry-leading products • AI accelerates Micron team members’ innovation and execution • Long-horizon R&D investments enhance Micron’s future competitiveness • Co-innovation with partners builds leadership solutions with Micron memory and storage at the core • Micron is positioned to extend technology and product leadership for the next decade and beyond 4 Accelerating intelligence to enrich life for all
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5 Agents call tools, data and other agents Each wave of AI increases memory demand Illustrative for concept: not to scale HBM capacity per GPU: NVIDIA product specifications (H100 SXM 80GB HBM3; Blackwell Ultra B300 288GB HBM3E). GB = gigabyte | GPU = graphics processing unit | HBM = high-bandwidth memory AI related demand spans every layer of the memory and storage hierarchy Training Models learn from internet-scale data HBM per GPU, H100 to B300 3.6x Inference & reasoning Models think before they answer, for billions of users memory per server in three years 2x Agentic AI AI context length growth per year 30x Physical AI Robots, vehicles, devices DRAM in L4+ robotaxi vs. today’s L2+ car >10x Bandwidth sets accelerator throughput Bandwidth for speed, capacity for context Persistent context at every memory tier Fast, efficient memory and storage at the edge
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6 Standard, custom and vertical HBM Training and real-time inference at the highest bandwidth High-capacity and low-power DRAM modules Active model context High-performance SSDs and AI-class NAND KV cache and context offload, attention High-capacity SSDs Training data, checkpoints, archives at scale Main Memory Context Memory Storage Networked Data Lakes Near Memory Autonomous vehicles Robotics and humanoids AI PCs Mobile HBM = high-bandwidth memory | KV = key-value | PC = personal computer | SSD = solid state drive Architecture evolving for AI workloads Micron’s portfolio spans the memory and storage hierarchy for the data center and beyond Data Center Memory Hierarchy
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7 Technology enables industry firsts & best-in-class products Claims of industry leadership, speed, and compactness apply at the time of announcement and are not ongoing claims. ASIL = Automotive Safety Integrity Level | DDR5 = fifth-generation double data rate | G9 = ninth generation | GB = gigabyte | HBM4 = fourth-generation HBM | LPDDR5X = low-power double data rate 5X | MT/s = megatransfers per second PCIe = peripheral component interconnect express | QLC = quad-level cell | RDIMM = registered dual in-line memory module | SOCAMM = small outline compression attached memory module SOCAMM2 = second-generation SOCAMM, standardized in JEDEC | SSD = solid state drive | TB = terabyte | UFS = universal flash storage Jun 2025 Shipped samples of 1γ-based 10.7 Gbps LPDDR5X Jan 2026 Shipped 3610 SSD: Industry-first PCIe Gen5 G9 QLC client SSD Feb 2026 Shipped 9650 data center SSD: World’s first Gen6 SSD in mass production May 2026 Shipped 245 TB 6600 ION: World’s highest-capacity data center SSD Sep 2026 Sampled 512 GB DDR5 RDIMM: World’s first ultra-dense module, up to 9,200 MT/s Mar 2026 Announced HBM4 36 GB 12-high high-volume manufacturing Mar 2026 Sampled 256 GB SOCAMM2: Industry’s highest-capacity LPDRAM module Aug 2026 Qualified ASIL-B UFS 4.1: World’s first ASIL-B UFS 4.1 for automotive Mar 2025 Shipped industry-first SOCAMM module
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LLM inference Inference raises the bar for memory technology Prompt Your question and relevant context Answer Response generated one token at a time Memory and storage innovation drive AI performance → → Saved calculations (KV cache) Low-power DRAM modules Energy-efficient working capacity* First token from prefill Then one token per decode step HBM feeds the processor repeatedly Storage (SSDs) Holds source information Retrieved when needed HBM feeds the processor repeatedly 1 Prefill Read the prompt 2 Keep Save calculations to reuse 3 Decode Read saved calculations per token *Role depends on system architecture. Simplified flow. Storage is not read for every token. Bottlenecks vary. AI = artificial intelligence | HBM = high-bandwidth memory | KV = key/value | LLM = large language model | SSD = solid-state drive
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9 Memory has never stopped scaling >400x more bits per DRAM wafer since 1995 At 1γ dimensions: >1,500 capacitors across the width of a 50 µm hair Bits per wafer 22 Micron DRAM nodes 1995 → 2026 350nm 210nm 130nm 78nm 42nm 25nm 20nm 1Xnm 1Ynm 1Znm 1α 1β 50 µm Human hair Source: Micron | GB = gigabyte | nm = nanometer | µm = micrometer 1γ
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10 Micron’s sustained technology leadership 1z First to volume production 1α Industry’s first shipment 1β Industry’s first shipment 1γ Industry’s first sample shipment HBM3E 8H volume production HBM4E samples to key customers G7 Industry’s first shipment G8 Industry’s first shipment G9 Industry’s fastest; first G9-based SSD 2019 2020 2021 2022 2023 2024 2025 2026 DRAM consecutive leadership nodes 3 consecutive generations performance and power leadership 3 consecutive leadership nodes 4 HBM NAND HBM4 12H shipments HBM3E 12H shipments Sources: Micron press releases: 1z (Aug. 15, 2019), 1α (Jan. 26, 2021), 1β (Nov. 1, 2022), 1γ (Feb. 25, 2025), G7 (Nov. 9, 2020), G8 (July 26, 2022), G9 (July 30, 2024), HBM3E (Feb. 26, 2024). 1z: first to mass-produce 16Gb DDR4 on 1z. 1γ: first to ship 1γ DDR5 samples. G9: first G9 TLC NAND shipped in an SSD. HBM3E power vs. competition at time of announcement. 12H = 12 layers of DRAM die | 8H = 8 layers of DRAM die | G7 = seventh generation | G8 = eighth generation | G9 = ninth generation | HBM = high-bandwidth memory HBM3E = HBM third generation, extended | SSD = solid state drive
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11 The pace of memory innovation If a Porsche 911 had evolved at the same pace as memory between 1995 and 2026… 1995 270 hp · $60,000 · 23 MPG 2026 2,700,000 hp · $5.00 · 23,000 MPG ≈ the power of 10 aircraft carriers Ratios applied to match each metric. Performance improvement is captured in the horsepower, cost improvement is captured in the price, and power efficiency is captured in the MPG. hp = horsepower | MPG = miles per gallon
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12 One HBM4 stack 2.8 TB/s HBM4 vs. worldwide internet bandwidth 2026 ~100 HBM4 stacks match worldwide internet bandwidth Worldwide internet bandwidth ≈ 282 TB/s 1 square = 1 stack (2.8 TB/s) 2026 internet: TeleGeography, total international internet bandwidth, mid-2026 = 2,259 Tb/s ÷ 8 = 282 TB/s. 282 ÷ 2.8 ≈ 100 stacks. HBM4: 2,048 bits × 11 Gbps ÷ 8 ≈ 2.8 TB/s. | Package image illustrative. GB = gigabyte | Gbps = gigabits per second | GPU = graphics processing unit | HBM4 = fourth-generation HBM TB/s = terabytes per second
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13 Memory has become the AI bottleneck Memory capability and architecture must evolve Memory shapes AI capacity, performance and cost per token AI workload Context windows, agents and reasoning at scale Compute FLOPS, utilization and stall time Memory Bandwidth, capacity and thermals Storage Capacity and cost per token FLOPS = floating-point operations per second 13
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14 • AI has created unprecedented opportunity for memory and storage; Micron has executed and delivered • Micron’s technology leadership is foundational to delivering differentiated, industry leading products • AI accelerates Micron team members’ innovation and execution • Long-horizon R&D investments enhance Micron’s future competitiveness • Co-innovation with partners builds leadership solutions with Micron memory and storage at the core • Micron is positioned to extend technology and product leadership for the next decade and beyond 14 Accelerating intelligence to enrich life for all
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15 Core technology leadership underpins future architectures Memory design features, performance and power are the differentiators DRAM The DRAM cell is nearing atomic limits So, DRAM must now build up Planar NAND Scaled until the release of 3D NAND in 2015 3D NAND z-scaling Same footprint, more bits with each layer 3D NAND xyz-scaling NAND 3D DRAMPlanar DRAM Shrinking cells and increasing layers
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16 DRAM roadmap: continuous scaling through innovation Micron is extending 6F² leadership and developing 3D DRAM; not pursuing 4F² due to increased complexity/cost ✓ EUV introduction U.S. manufactured Wafer bonding High-NA EUV ✕ Over two decades of 4F² technology investigation No viable scaling path 3D DRAM ✓ 3D DRAM development 3D2 Directional; no dates implied. Node names and phases subject to change. EUV = extreme ultraviolet lithography | High-NA = high numerical aperture 3D1 New materials 1δ Early development DevelopmentYield ramp 1ε ηÅ Pathfinding1γ ζÅIn high-volume manufacturing 6F² DRAM 4F² DRAM
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17 1δ: the world’s most advanced DRAM Fifth consecutive node of DRAM industry leadership – ramping in the second half of 2027 Industry-leading technology manufactured in the U.S. Supports differentiated HBM5, vHBM, vEIM products Leadership in power, performance and cost Enables next-gen LPDDR, DDR and graphics modules • Mid-20s percentage bit density improvement from 1γ; optimized cost • Angstrom-level process control • Equipment intelligence, new materials • Advanced HKMG CMOS • High-performance products • Next-generation mobile memory • High-density modules for AI workloads • Advanced TSV technology • Thermal-aware design CMOS = complementary metal-oxide-semiconductor | DDR = double data rate | HBM = high-bandwidth memory | HKMG = high-k metal gate | LPDDR = low-power double data rate TSV = through silicon via | vEIM = vertical edge inference memory | vHBM = vertical HBM
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18 DRAM CMOS logic roadmap and performance through 2030 Accelerated CMOS enabling future differentiated product requirements >10x CMOS logic performance Poly SiON → 2nd Gen 3D CMOS • Foundation of Micron’s AI memory leadership • Multiple nodes of power and performance leadership • Advanced CMOS roadmap to meet AI bandwidth demands 10 30 50 70 90 110 130 150 170 Gen2.2 Gen2.3 Gen3.5C Gen3.5W Gen5W Gen 7W Gen 8W Poly SiON 1st Gen HKMG 2nd Gen HKMG 3rd Gen HKMG 1st Gen 3D CMOS 2nd Gen 3D CMOS CMOS = complementary metal-oxide-semiconductor | HKMG = high-k metal gate Performance 2020 2030 >10x
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19 Next-generation DRAM for AI More bandwidth and capacity, with greater power efficiency Performance improvements are targets. 1 TB RDIMM is a capability, not a product commitment. DDR5 = fifth-generation double data rate | DDR6 = sixth-generation double data rate | LP6 = low-power double data rate 6 | LP5 = low-power double data rate 5 | RDIMM = registered dual in-line memory module | TB = terabyte LP6 for data center and mobile >35% Improved power vs. LP5 High-reliability DDR6 for server >2x Bandwidth vs. DDR5 High-capacity RDIMM 1TB Memory capacity
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20 Building on HBM leadership to drive AI performance Each architecture step shortens the memory–compute path to deliver more tokens per watt Compute Base Die Base Die Standard HBM Industry baseline Memory beside compute on an interposer Compute Custom HBM Co-designed with customers Base-die logic adds differentiated features Compute Vertical HBM (vHBM) Memory stacked on compute Shortest memory–compute path Custom base die Core memory logic= + Compute logic Higher bandwidth per watt · More tokens per watt HBM = high-bandwidth memory
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21 Advanced packaging innovations enable future HBM Next-generation memory-compute architectures leverage novel packaging innovations Interconnect density Stacking technology Thermal innovations • TSV and µbump scaling • Hybrid copper bonding • Metallurgy innovations • 16H µbump and hybrid stack • Bandwidth and thermal improvement • 2.5D HBM + 3D vHBM integration • Heat spreader over PHY • Front and backside innovations • Thermally aware design HBM Interposer GPU HBM Interposer GPU vHBM Die-die no gap GPU = graphics processing unit | HBM = high-bandwidth memory | PHY = physical layer | TSV = through silicon via | vHBM = vertical HBM
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22 Token efficiency scales with bandwidth, energy efficiency, capacity Product roadmap expands to custom HBM, vHBM and vEIM Token efficiency = Bandwidth + Energy efficiency + Capacity HBM4 HBM4E HBM5 HBM5E HBM6 vHBM 1 vHBM 2 vHBM 3 vEIM 1 vEIM 2 vEIM 3 2026 2027 2028 2029 2030 vHBM and vEIM enablers Packaging Hybrid bonding Higher stack density and finer interconnect pitch Thermals Advanced thermals Lower thermal resistance and better heat spreading as power rises JEDEC + custom + 3D Base die, PHY , packaging and workload optimized together Token-efficiency positions are illustrative. Product timing represents targeted high-volume manufacturing; timing and performance targets are directional and subject to change. HBM = high-bandwidth memory | JEDEC = Joint Electron Device Engineering Council | PHY = physical layer | TB/s = terabytes per second | vEIM = vertical edge inference memory | vHBM = vertical HBM System co-design vHBM Vertical 3D HBM HBM JEDEC + custom beginning with HBM4E vEIM Vertical edge inference memory vEIM 1 specs: 2 TB/s bandwidth <1 pJ/bit energy
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23 G9 NAND Industry leading technology supporting a broad portfolio Scale Today • ~2x bit density vs. G9 • Up to 1.5x I/O speed • >25% less data transfer energy per bit vs. G9 Leap Ahead G11 NAND 5 10 15 20 25 30 35 40 45 G7 (N140) G8 (N150) G9 (N160) G1X (N170) NAND density (Gb/cm2) G11: the world’s most advanced NAND • Wafer-on-wafer bonding • >400 layers and industry-leading cell pitch • Volume ramp in 2H 2027 Beyond G11: redefining the limits • Breakthrough high-mobility material • Ultra dense cell architecture • Energy-efficient devices and data paths Proven leadership extends with G11 generational leap Each generation of NAND technology leadership builds on the last G7 G8 G9 G11 Gb = gigabit
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24 Micron AI-class NAND design optimized for AI workloads AI-class NAND architected to accelerate emerging AI workloads and applications NEAR-COMPUTE BANDWIDTH High-IOPS SLC NAND designs for GPU-initiated, small-block data access beyond system memory Emerging use cases Vector search High-bandwidth AI-class NAND TSV-stacked NAND with a logic base die, enables high-capacity tier close to the accelerator Emerging use cases FINE-GRAINED ACCESS High-IOPS AI-class NAND More data closer to compute improves utilization, scalability and system efficiency Model weights Long context KV cache IOPS = input/output operations per second | SLC = single-level cell | TSV = through silicon via AI context accessGraph analytics
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25 Micron future AI-optimized storage solutions Automotive, Robotics, Mobile and Wearables AI-class NAND enables purpose-built storage solutions wherever AI data lives Maximize AI throughput Keep accelerators fed with massive data sets held closer to compute Next-generation SSDs High-performance, high-capacity (up to 512TB) High-IOPS 25M–100M IOPS small-block access AI acceleration Optimized accelerator data pipelines Power private, local AI High-bandwidth, power-efficient storage for private and on-device inference On-prem services High-capacity, low-latency private AI Workstations Model loading, fine-tuning, creation AI PC Power-efficient local AI across devices Scale AI to the edge Compact, low-power, high-bandwidth storage for AI in the physical world Automotive Intelligent cockpits and driver assistance Humanoid robotics Real-time perception and context retention Mobile and wearables Low-power on-device AI and immersive AR On-prem and AI PC Data Center and AI infrastructure Automotive, robotics, mobile and wearables AR = augmented reality | IOPS = input/output operations per second | PC = personal computer | SSD = solid state drive | TB = terabyte
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26 • AI has created unprecedented opportunity for memory and storage; Micron has executed and delivered • Micron’s technology leadership is foundational to delivering differentiated, industry leading products • AI accelerates Micron team members’ innovation and execution • Long-horizon R&D investments enhance Micron’s future competitiveness • Co-innovation with partners builds leadership solutions with Micron memory and storage at the core • Micron is positioned to extend technology and product leadership for the next decade and beyond 26 Accelerating intelligence to enrich life for all
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27 AI makes Micron 2x faster: invention to volume production Industry-leading use of AI across development teams; two examples included below Data Center SSD controller 2x faster to silicon tape-out with AI Data Center SSD product >2x faster to silicon ready for customer releases with AI Micron internal program data. Prior generation vs. new generation development time. IP = intellectual property | RTL = register transfer level | SSD = solid state drive Months to silicon tape-out Months to silicon ready for customer releases AI use • AI-agent RTL and verification • GenAI IP porting • AI root-cause analysis • AI physical design AI use • AI-generated firmware • AI root-cause analysis • Smart test selection • Coverage agents Prior generation New controller Prior generation New product 50% less time 60% less time
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28 • AI has created unprecedented opportunity for memory and storage; Micron has executed and delivered • Micron’s technology leadership is foundational to delivering differentiated, industry leading products • AI accelerates Micron team members’ innovation and execution • Long-horizon R&D investments enhance Micron’s future competitiveness • Co-innovation with partners builds leadership solutions with Micron memory and storage at the core • Micron is positioned to extend technology and product leadership for the next decade and beyond 28 Accelerating intelligence to enrich life for all
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29 Long-horizon R&D investments Investing in capabilities for long-term leadership and a greater role in shaping the future 3-10 YEARS Micron Ventures $550M total capital commitment Investing across the AI stack to strengthen ecosystem engagement 5-10 YEARS Albany NanoTech + NY CREATES Accelerating the high-NA EUV and lithography roadmap 10+ YEARS Micron Research Labs planned over the next decade First dedicated memory research hub in the U.S., looking beyond a 10-year horizon Building the next generation of memory researchers and technology leaders Separately, Micron has committed more than $250B to manufacturing and R&D across the United States. EUV = extreme ultraviolet lithography | High-NA = high numerical aperture | NY CREATES = New York Center for Research, Economic Advancement, Technology, Engineering and Science $10BAdvanced lithography
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30 Micron and ecosystem leaders create customer advantage Solving customer challenges through memory and storage innovation, from startups to hyperscalers ¹ WEKA NeuralMesh data reduction, assuming 3:1. Results depend on configuration and workload. Meta X Micron Joint Whitepaper: LPDDR6: A Scalable, Power-Efficient Memory for Data Centers EB = exabyte | LPDDR6 = low-power double data rate 6 | PB = petabyte | SSD = solid state drive | TB = terabyte >1.1 EB 1 in a single rack Micron 6600 ION 245TB SSDs deliver 15.8PB per 2U server Customer challenge AI data growth is outpacing finite rack space, power and cooling Joint solution • Engineering-level SSD and platform optimization preserves power and space for more compute. • Delivers more than 2.1x throughput density vs. competitors.1 LPDDR6 for data center systems Performance • capacity power-efficiency • reliability Customer challenge Power efficient scaling of memory bandwidth is a primary need for advanced compute and AI What we are delivering • Advancing LPDDR6 as data center-class memory architecture • Meta platform and application expertise combined with Micron memory innovation for fleet-scale optimization. + +
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31 Co-innovation delivers scaled solutions to meet AI demand One ecosystem, building leadership solutions together, with memory at the core CSP = cloud service provider | EDA = electronic design automation | IP = intellectual property Micron + customers Translate AI workloads into new memory architectures Micron + customers Micron + ecosystem Create new bonding, thermal, interconnect, IP, material, process and test capabilities Micron actively developing custom products with multiple CSPs One connected ecosystem Micron, customers and partners qualify solutions together Micron Deliver qualified, high-volume customer solutions Optimize base die, DRAM, interfaces, power and packaging Leverage AI design workflow with EDA vendors Co-design with foundry partners Co-imagine Co-design Co-develop Co-validate Deliver at scale
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32 • AI has created unprecedented opportunity for memory and storage; Micron has executed and delivered • Micron’s technology leadership is foundational to delivering differentiated, industry leading products • AI accelerates Micron team members’ innovation and execution • Long-horizon R&D investments enhance Micron’s future competitiveness • Co-innovation with partners builds leadership solutions with Micron memory and storage at the core • Micron is positioned to extend technology and product leadership for the next decade and beyond 32 Accelerating intelligence to enrich life for all
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© 2026 Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Statements regarding products, including statements regarding product features, availability, functionality, or compatibility, are provided for informational purposes only and do not modify the warranty, if any, applicable to any product. Drawings may not be to scale. Micron, the Micron logo, the M logo, Intelligence Accelerated , and other Micron trademarks are the property of Micron Technology, Inc. All other trademarks are the property of their respective owners.