Ladies and gentlemen, good afternoon. At this time, I'd like to welcome everyone to QuickLogic Corporation's Fiscal First Quarter 2025 earnings conference call. As a reminder, today's call is being recorded for replay purposes through May 20, 2025. I'd like to turn the conference over to Ms. Alison Ziegler of Darrow Associates. Thank you. You may begin. Thank you, Operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited to statements regarding our future profitability and cash flows, expectations regarding our future business, and statements regarding the timing, milestones, and payments related to our government contracts, and statements regarding our ability to successfully exit SensiML. Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time-to-market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could disrupt supply or delivery of or demand for the company's products, and changes in tax rates and exposure to additional tax liabilities. Actual results or trends may differ materially from those discussed today. For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic's most recent filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IRA web page that provides current and historical non-GAAP data. Please note QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared marks we made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian. Thank you, Alison. Good afternoon, everyone, and thank you all for joining our First Quarter 2025 Conference Call. Last quarter, I said that we expected to be awarded the first of two eFPGA hard IP contracts for Intel 18A designs within weeks, and the second one very shortly after that. I forecasted the combined value would be mid-seven figures and, if awarded in the expected timeframe, that the revenue would be recognized in Q2. The first of these contracts was awarded a few weeks ago after our last conference call, and on April 28, we announced that we delivered design-specific eFPGA hard IP for the customer's Intel 18A test chip. The second contract is with the same customer, but for a different program. The customer has advised us that it has been awarded funding for the program, but funding for the production ASIC, which is a subcomponent of the program, will not be awarded until Q4. Due to this delay, our revenue guidance for Q2 is $4 million. While disappointing, it does not change our full-year outlook for solid revenue growth, non-GAAP profitability, and positive cash flow. Let's take a moment to discuss the test chip program. Given the fact Intel 18A is a new process and incorporates some state-of-the-art features such as PowerVia backside power delivery network that we are using in our eFPGA hard IP, we determined having a test chip would be a good investment. To do a test chip on our own would have cost millions of dollars, so we contributed our eFPGA hard IP license in kind for access to the customer's test chips. These test chips will enable us to fully characterize the power consumption and performance, which enables lead prospective customers to lower their risk assessment of our eFPGA hard IP on Intel 18A silicon. As it has turned out, just the delivery of our design-specific eFPGA hard IP and having a test chip heading into fabrication this summer has given some prospective customers confidence to accelerate their engagements. Our rapid delivery of the design-specific eFPGA hard IP for the test chip has also brought us closer to this key customer. As a matter of fact, during a high-level meeting with the customer in early May, a third design for a chiplet fabricated using Intel 18A was outlined that we hope to secure later this year. We have invested heavily to gain our unique position as the first available source for eFPGA hard IP for Intel 18A, and Intel Foundry has acknowledged our work and progress. Last summer, we announced that we joined the Intel Foundry Accelerator IP and US MAG Alliances, and we have recently been named a partner in the Intel Foundry Accelerator Chiplet Alliance. As some of you are aware, I was invited by Intel Foundry to present from the main stage at Intel Foundry Direct Connect 2025. This was quite a unique honor in that QuickLogic was one of only four companies to present in the ecosystem spotlight to an audience of more than 1,000 people. The other three were Cadence, eMemory, and Synopsys. Intel Foundry has published a video of the QuickLogic presentation on the Intel YouTube channel. We will post a link to the video in our blog following this call. My presentation was very well received, and the news that QuickLogic has delivered design-specific eFPGA hard IP for a customer's Intel 18A test chip was recognized as a significant milestone. The excitement and anticipation for Intel 18A was palpable. Intel Foundry confirmed Intel 18A is in risk production, with Panther Lake scheduled for mass production by year's end. Intel Foundry also provided a clear roadmap forward from Intel 18A, its strategy to address both US MAG and commercial markets, and its rapidly developing initiatives for advanced packaging and chiplets. In addition to Intel Foundry painting a very optimistic picture about its progress and future outlook, there was increased participation by alliance partners demonstrating IP, EDA, and services for Intel 18A, as there were at Intel Direct Connect 2024. In short, Intel 18A is ready for prime time, and there is significant interest in the unique value proposition our technology enables. Our value proposition is integration, which is what has driven the growth of the semiconductor industry since the invention of the integrated circuit 65 years ago. By using our unique EFPGA hard IP, design engineers can integrate the benefits of a discrete FPGA by embedding it in their ASIC and SoC designs or with a chiplet solution. As it stands today, we are the only company offering EFPGA hard IP for Intel 18A technology that enables this integration. Pairing a discrete FPGA with an ASIC or SoC is very common in US MAG designs, where the total market for discrete FPGA devices is approximately $1.5 billion. The defense industrial base is intently interested in using Intel 18A for new designs, and their frequent use of FPGA technology bodes very well for our unique position. While capitalizing on this interest is a strong focus, we are also rapidly building momentum in various commercial markets, including several new Intel 18A opportunities. On April 24, we announced the inclusion of our EFPGA hard IP in the new Faraday FlashKit- 22R RAM SoC development platform. This is the UMC 22-nanometer design win we announced in November of 2023 and have been tracking the progress in our quarterly conference calls. Faraday is a Taiwan-based semiconductor company with a market capitalization of approximately $1.5 billion. Its core business model is to help its customers develop ASIC and SoC designs and then storefront those designs. In the course of its business, Faraday has seen a number of its customers pair a discrete FPGA with the ASIC or SoC that Faraday designs for them. The important point to embrace here is the primary purpose of an ASIC or SoC is to integrate as many discrete chip functions as possible into a single device, and our IP enables that integration to include discrete FPGA devices. To enable its customers to realize the many benefits of FPGA integration, Faraday introduced its new SoC development platform, which includes our eFPGA hard IP. This enables Faraday's customers to easily transition from a two-chip solution, an ASIC or SoC paired with a discrete FPGA, to a single-chip solution of embedded FPGA inside the ASIC or SoC. We believe this platform will generate production eFPGA hard IP license revenue beginning in the second half of 2025 and royalty revenue in future years. We believe there will be opportunities to expand our involvement with Faraday going forward. Notably, Faraday was one of three companies that was prominently displayed at Intel Direct Connect as a value chain alliance partner. There are four important takeaways from these data. One, Faraday's focus on commercial applications will help accelerate our expansion into new end markets. Two, Faraday's success underscores the industry demand for and value of a storefront business model. Three, our IP enables the integration of discrete FPGAs that are often paired with ASIC and SoC devices. We believe this is a meaningful subset of the $12 billion discrete FPGA market. Four, the Faraday development platform is likely to win many unique customer designs that will generate IP license and royalty revenue for QuickLogic that will scale very favorably. We announced the fourth award of the Strategic Radiation-Hardened FPGA government contract, valued at approximately $6.6 million last December. Following that, about six weeks ago, we announced an additional $1.4 million incremental funding modification, which extends the fourth tranche. We have requested permission to share some details about the expanded scope of this contract with our investors, but so far that permission has not been granted. That said, I can tell you the device we are developing addresses a number of strategic and space applications where total dose and single-event radiation hardness is critical, and the designs must include the flexibility only FPGA technology can provide. As a matter of fact, several customers have already expressed interest in using the resulting design via QuickLogic storefront once it is completed. Now let me take a moment to update our progress on existing contracts that are scheduled to contribute to our EFPGA hard IP revenue in 2025 and beyond. A number of these contracts have achieved significant milestones during the last several months. These include tape-out and, in several cases, test chips that have been completed and are in validation. This is important because, in some cases, test chip validation will lead to an IP production license and, in a few cases, new EFPGA hard IP contracts. These are also good illustrations that a long tail of revenue is commonly attached to our EFPGA hard IP contracts, and following that, a stream of royalties or storefront revenue that can extend for years and, in some cases, more than a decade. Let's start with the IP contracts. Our first contract targeting the GlobalFoundries, or GF's 12LP fabrication node, is with a defense industrial-based customer and includes two cores. We completed our initial deliverables for the first core during Q3 and the second core during Q4 of 2024. In accordance with the forecast I shared last quarter, we had nominal revenue recognition in Q1 and anticipate similar revenue recognition in Q2 in support of the customer's test chip development. Last quarter, we announced an EFPGA hard IP contract with a new defense industrial-based customer valued at $1.1 million that will also be fabricated on the GF 12LP node. Due to the fact we already had EFPGA hard IP established for that node, we will recognize revenue and record cash flow in Q2 and Q3 2025. Our first contract for TSMC's 12-nanometer fabrication node is with a large, well-known international company. This design is for a new ultra-low-power SoC targeting a variety of commercial and industrial IoT AI applications. The customer is currently evaluating test chips, and we expect a decision about a second SoC design during Q2. In September 2023, we announced a leading technology company chose our eFPGA hard IP for a design that will be fabricated using GF's 22FDX platform. Test chips have been received and are in evaluation. If all goes as planned, we anticipate revenue recognition of a production license during the second half of 2025. The following are IP services contracts that we believe will be supplied via our storefront program. In November 2022, I shared that we taped out a new device for a customer that incorporates our eFPGA hard IP. While we remain in a holding pattern due to a delay with one of the customer subcontractors, we continue to believe we will resume work during the second half of 2025 and that this design has very substantial storefront potential starting in a couple of years. In addition to this initial contract, we have engaged with this customer on multiple new ASIC and chiplet design opportunities that incorporate our eFPGA hard IP. Last quarter, we also announced the award of the first phase of what we expect will be a seven-figure direct-to-storefront eFPGA hard IP contract with another new defense industrial-based customer. This application, which enables low-power processing of changing algorithms, is perfectly suited for our eFPGA solution. We completed our deliverables for the first phase of this contract and expect to be awarded the next phase in the second half of 2025. We anticipate design services and IP revenue recognition could begin in Q3 and carry into 2026. Following that, we expect storefront revenue could begin as early as 2027. While some of our existing contracts have good storefront potential that may materialize earlier, this is our first direct-to-storefront contract. Turning now to chiplets. There are two distinctly different chiplet markets. The vertical market is where you see activity today and where we have some chiplet contracts with others pending. In most cases, a single company controls all of the devices in vertical markets. These include processors sold by AMD, Intel, NVIDIA, and others, and end customers that use chiplets in conjunction with an ASIC or SoC. We have done well in the ASIC and SoC markets and believe we will continue to win new contracts for vertical market chiplet designs. The other chiplet market is the commercial off-the-shelf or COTS market. In this market, semiconductor companies will develop and sell chiplets that comply with industry standards as mostly catalog devices. These standards are in development and are forecasted to begin rolling out in 2026. This is the market your chip will address with a variety of devices, including parts that incorporate our eFPGA hard IP. Companies that want to participate in the COTS market are anxious to develop devices, but most see the risks of doing that ahead of standards as being too high. We are in early discussions with some potential customers regarding a digital proof of concept that would mitigate the risks of a physical design and give them a head start once standards are solidified. Here, we are leveraging the power of our proprietary software tools in an innovative way that we believe will generate revenue ahead of standards, give us a foot in the door, and help our customers get a jump on the market. Our distributors continue to perform very well. During the quarter, we saw an increase in both device and IP engagements, and even though design cycles are generally long, we believe some deals will close in the second half and generate revenue this year. Last quarter, we announced that our board of directors is actively exploring options for SensiML, and there were preliminary discussions regarding the possible sale of this subsidiary or its assets. Due diligence is ongoing, so I can't comment other than saying that our full-year outlook for solid growth and profitability does not include any contributions from SensiML. With that, let me now turn the call over to Elias for a review of the financial results, and I will rejoin for our closing remarks. Elias, please go ahead. Thank you, Brian, and good afternoon, everyone. Total first-quarter revenue was $4.3 million, an approximately $300,000 above the midpoint of our guidance range. This upside was driven by a customer that pulled in new product shipments to Q1 that were previously scheduled for Q2. Total revenue was down 28% from Q1 2024 and down 24% compared to Q4 2024. New product revenue in Q1 was $3.8 million, down 23% from Q1 2024 and down 19% compared to Q4 2024. Mature product revenue was $0.6 million, down from $1.1 million in the first quarter of 2024 and $1 million in the fourth quarter of 2024. The decreases in total revenue and new product revenue from prior periods were mostly due to the timing of certain large eFPGA IP contracts. Non-GAAP gross margin in Q1 was 45.7%. This was below the midpoint of our outlook due to the fact approximately $300,000 of R&D costs that we projected would be allocated to OpEx were allocated to COGS. This compared with Non-GAAP gross margin of 71.3% in Q1 2024 and 62.9% in Q4. Non-GAAP operating expenses in Q1 were approximately $3 million. This was approximately $200,000 below the midpoint of our outlook and due to the COGS allocation I just mentioned above. This compares with Non-GAAP operating expenses of $2.5 million in the first quarter of 2024 and $2.9 million in the fourth quarter of 2024. Non-GAAP net loss was $1.1 million or $0.07 per diluted share. This compares to Non-GAAP net income of $1.7 million or $0.12 per diluted share in Q1 2024 and a Non-GAAP net income of $0.6 million or $0.04 per share in the fourth quarter of fiscal 2024. The difference between our GAAP and Non-GAAP results is related to non-cash stock-based compensation expenses and restructuring costs. Stock-based compensation for Q1 was $0.9 million and restructuring costs for Q1 were $0.1 million. Stock-based compensation was $1.6 million in Q1 2024 and $0.9 million in Q4 2024. For the first quarter, one customer and one distributor accounted for 10% or more of total revenue. At the close of Q1, total cash was $17.6 million, inclusive of a $15 million credit facility. This compares with $21.9 million inclusive of an $18 million credit facility at the close of Q4 2024. The primary driver for cash use during Q1 was the timing of payments to our subcontractors for the strategic Rad-Hard FPGA contract. Additionally, changes in accounts receivable, contract assets, and accounts payable resulted in a little more than $1.1 million in cash usage. Also contributing to cash usage were continued investments to develop eFPGA hard IP for Intel 18A ahead of orders and the integration of Synopsys Synplify in Aurora PRO. We completed the integration of Synplify into Aurora Pro and, setting aside some modest costs for further refinements, completed our development of Intel 18A hard IP during Q1. While these were significant investments, we believe they will produce very impressive ROI going forward. As Brian noted, we are currently the only source for eFPGA hard IP for Intel 18A and have delivered design-specific IP for customers' test chip. With this unique position, we anticipate winning production contracts in 2025 and beyond. Going forward, we do not anticipate developing eFPGA hard IP for new fabrication processes ahead of contracts that fully fund the development costs. During the first quarter, we raised approximately $1.5 million from institutional investors in a registered direct offering, as well as $1.2 million net from the ATM we announced last March. While the ATM remains in place, we have not utilized it since it was paused ahead of a registered direct offering. Now moving to our guidance and outlook for the second quarter of fiscal 2025, which will end on June 30th. Revenue guidance for Q2 2025 is approximately $4 million, plus or minus 10%. Second quarter revenues are expected to be comprised of approximately $3.4 million in new products and $0.6 million in mature products. As Brian stated in his remarks, the lower-than-anticipated Q2 revenue guidance is attributable to the delay of a large IP contract that we currently anticipate will be awarded in Q4 2025. Based on the anticipated Q2 revenue mix, Non-GAAP gross margin for the second quarter is expected to be approximately 50%, plus or minus 5 percentage points. The lower gross margin is attributable to the unfavorable absorption of fixed costs due to lower revenue. With the significant revenue rebound we anticipate beginning in Q3, we are modeling a full-year Non-GAAP gross profit margin will be in the low 60% range. Our Q2 Non-GAAP operating expenses are expected to be approximately $3 million, plus or minus 5%. We are modeling Non-GAAP OPEX to be approximately $3 million per quarter during the second half of 2025. Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. The classifications are mainly related to labor and tooling for our IP contracts with customers. This may cause variability in our quarterly gross margins and operating results that will usually balance out on the operating line. After interest and other income, we currently forecast that our Q2 Non-GAAP net loss will be approximately $1.1 million-$1.2 million or $0.07-$0.08 per share. The difference between our GAAP and Non-GAAP results is related to non-cash stock-based compensation expenses. In Q2, we expect the compensation will be approximately $0.9 million. This is the same as Q1 2025 and up $100,000 from Q2 2024. As a reminder, there will be movements in our stock-based compensation during the year and it may vary each quarter based on the timing of grants. We are anticipating Q2 cash flow from operations to be relatively flat and our scheduled payments to subcontracts for SRH contract are approximately 50% lower than they were during Q1. While having the aforementioned ATM in place provides us with flexibility, we are not currently planning to access it during Q2. As Brian noted earlier, for the full year 2025, we are anticipating solid revenue growth, Non-GAAP profitability, and positive cash flow. Thank you. With that, let me now turn the call back over to Brian for his closing remarks. Thank you, Elias. As I mentioned earlier, I was selected by Intel to present the QuickLogic story from the main stage at Direct Connect 2025. My presentation was very well received, and based on the feedback we were given, gave our core value proposition a huge shot of credibility. If you boil down our value proposition to just one thing, that thing would be enabling integration. That is what has driven the semiconductor industry since the IC was invented 65 years ago. Our primary target markets are designs that would typically have a discrete FPGA sitting next to an ASIC or SoC. That is a very common practice in US MAG designs where discrete FPGA revenue was approximately $1.5 billion in 2024. This market opportunity, the very high qualification costs DIBs have for every discrete device and their intense focus on SWaP-C, size, weight, area, power, and cost, are the reasons we prioritized US MAG as we built our foundation for eFPGA hard IP. If you review the Faraday website, you'll see this pairing of a discrete FPGA with an ASIC or SoC is also more common than you might think in commercial designs. We believe the Faraday FlashKit development platform that integrates our eFPGA hard IP in its SoC will lead to a number of contracts in commercial markets. Also intriguing to note about Faraday's success is its very tight focus on storefront. Faraday manages storefront services for the vast majority of its contracts and with that reported nearly $500 million in revenue over the trailing 12 months. To be clear, our sales through Faraday to its customers will be eFPGA hard IP contracts. However, we believe a growing number of our direct IP customers will have interest in QuickLogic handling storefront services. As a matter of fact, we booked our first direct-to-storefront contract earlier this year, and we have several contracts we believe will end up being storefront. We see this as a trend for QuickLogic. As we have tried to outline for you in this call, 2025 has started out more slowly than we anticipated. However, beneath the numbers, momentum is building rapidly, and we are confident that we will post solid revenue growth, Non-GAAP profitability, and positive cash flow for full year 2025. Not only that, we also believe we will build momentum throughout the year to set us up for solid growth for years to come. Thank you. I'd now like to open the call for questions. Great. Thank you. We'll now be conducting a question-and-answer session. If you'd like to ask a question, please press * 1 on your telephone keypad. A confirmation tone will indicate your line is in the question queue. You may press * 2 to remove yourself from the queue. For participants using speaker equipment, it may be necessary to pick up your handset before pressing the * keys. One moment, please, while we pull up for questions. First question here is from Quinn Bolton from Needham & Company. Please go ahead. Hey, guys. Thanks for taking my question. Just Brian, maybe just walk us through the ramp of Intel 18A. You guys have done a couple of test chips now. As that starts to move to a production, is your revenue stream mostly just royalties on the customer solution? Can you also just address, is this customer starting in commercial markets? Is it more of a defense aerospace application? I have a follow-up. Thanks. Hey, Quinn. The audio is a little garbled, but I think if I repeat the question, you're asking about sort of the progress of Intel 18A in general and our timing of different IP that we've done for that leading up into revenue and royalties in the future. Is that right? Yeah, that's right. Sorry for the background noise. Okay. Yeah. I guess if we rewind a year when we first got access to the PDK version 1.0, this was definitely the first time that we've designed something on this modern of a process technology. This is sort of state-of-the-art. Definitely took a lot from our team to get that going. A lot of EDA tools, a lot of focus on that. Once we had it ported to that technology, we started to appreciate some of the capabilities of it, like the PowerVia backside power that I mentioned earlier. That was one of the bases of our presentation at the Intel Direct Connect last week or two weeks ago. We realized that you could actually, we got a really good IP core out of this in terms of power and die size because of those capabilities that we took advantage of. I think that as we started engaging more primarily with the defense industrial base, they're looking for things that are, I would say, further down the TRL curve than just paper tigers or PowerPoint. When I say TRL curve, I'm talking about technology readiness level. It's from 1 to 9. One is your paper simulations and nine is your in-flight on things. By us participating in this test chip that we've talked about, this actually helps accelerate further down the TRL curve in the eyes of prospective customers, especially defense industrial-based ones. I think that that was sort of the tipping point where we're able to carry these additional customer conversations forward into more timing-related discussions, commercial-related discussions, and understanding when they're planning to tape out their own test chips. I think that's all to say that we do have 18A license revenue forecasted this year, this fiscal year. Not just that one that we mentioned that's shifted to Q4, but even before that from some other customers, including commercial ones that are, I think, reviewing 18A as far enough along that it's worth pursuing from them for the ASIC that they might be developing because it's de-risked in their mind. I think the last part is just how does that map out to revenue and royalties for QuickLogic? That would be second half of this year, not just that Q4 one that we talked about specifically, but other ones that we have not talked about in so much detail on these calls, perhaps even coming in before that now in terms of licensing, which would be IP license revenue in this fiscal year and then royalties probably next year when they would actually get test chips out and then convert it over to production chips. They're not waiting at this point for Intel to be further along with the process. I think the fact that Intel last week at the conference said they're in risk production, even on their own Panther Lake processor, kind of shows that it's good enough for production in many cases. I'm glad we started a year ago. I think a lot of people were skeptical about starting so early in a process such as that, but I'm glad we did it. We're the only one with that EFPGA hard IP now. The more people see EFPGA and they start looking at their own ASICs and they're wondering, "This is a huge development cost and a huge development effort. How do we de-risk this ASIC?" Embedded FPGA, as you know, Quinn, is a great way to de-risk system design because you're building in flexibility for that own product. It also builds in a lot of flexibility for N+1, N+2, N+3 products that you can address with that same die because of that inherent flexibility now. We're excited, as you can tell from my answer here. Yeah, yeah. No, definitely. The value of the test chip, my guess is it's a certain size fabric that you're testing out on the test chip. The fact that you're just testing out a sort of given size fabric is enough to convince other customers that says, "Hey, this is real. It's working." If we change the size or the configuration, it's still enough in terms of their eyes to sort of give them the confidence to move forward on new designs. It absolutely is because once you prove out a common denominator for the logic and the routing and the memory and the DSP blocks, most customers believe that if you can do that for that size, that if you need to stamp and repeat a bigger array size for them, that we can do that. They know that that's sort of our model with Astrolis. We're sort of making almost like a memory compiler out of it for FPGA technology. Once we prove out the first one for power and timing, that's all stamp and repeat for bigger array sizes. The beauty of our model is we can do that in a matter of weeks, which is well within the cycle of what they need to do for an 18A type ASIC. Got it. The second question I had is just you guys are looking for profitability for the full year, obviously a strong revenue ramp. Just wondering if you could kind of what are the two or three maybe biggest drivers of that revenue ramp through the year? Obviously, you've talked about Intel 18A revenue. You've talked about the RadArm contract. What are just the key programs that drive that nice revenue growth into the second half? Thank you. Yeah, I can take that. Our base business that's here every quarter is our ongoing anti-fuse FPGA business, what we call mature products, and then the strategic RadArm contract. With that contract that we signed for the RadArm contract last December and then the incorrect funding modification that was added on top of that in the last few months, we have good visibility of that program for the rest of this year. The new revenue, the new wins driving the strong second half growth, we are forecasting to come from these IP contracts, some of which are just IP and some of which are storefront. I think this, again, if you look back in history the last five years, you go, "That's going to be a lot of designs you need to close to get to that number." If you drill into, "Okay, in the last year, you've come out with two 12-nanometer process ports, and now you've got this one for Intel 18A." All of those have substantially higher average selling prices than the stuff that we were doing years ago on 22 and more mature nodes. You do not have to close a lot of designs to get strong revenue growth. Like I was just answering on your first question, we are seeing a lot of strong interest on Intel 18A now, now that people realize that we're done with the first port. Those have substantial price increases or price that the value of those is much higher. We are seeing a handful of designs, again, both on 12-nanometer and 18A driving that second half revenue growth. Very well manageable within the team size that we have, again, because we have this whole notion of Astrolis being a very automated way of taking the port that we have done and then adapting it for customer and design-specific IPs that we need to come out with. Thanks. Thank Thank you, Brian. Thank you a lot. Thanks, Quinn. Next question is from Rick Neaton from Rivershore Investment Research. Please go ahead. Hi, Brian. Hi, Elias. Thanks for taking my questions tonight. My first question is, you mentioned in your closing remarks, Brian, about several storefront opportunities. We know about one, which is the direct-to-storefront you announced. You've also mentioned that the strategic RadArm contract could lead to storefront. Can you provide any color on what other opportunities you have for storefronts percolating in your funnel or in the itemized list of projects you've already provided? Sure. Just to add one more to that list that you gave there, Rick, we have the November 2022 tape-out customer. Between that and this more recent one that we just announced on the last call, the direct-to-storefront, and then, of course, the biggest of which is the strategic RadArm opportunity, those are contracted ones. If we move to things in the funnel, we have a handful of ones that we've either proposed through the government RFP process where people are looking at seeding different technologies to help build a chiplet ecosystem. We have that. Are ones that have come about now since at the Intel conference, they launched their own chiplet alliance or ecosystem. We are one of the founding members of that. There has been a lot of interest coming out of that for chiplets that are now part of our funnel. I think because, again, we have IP ready now on 12 and 22 and now 18A, we can actually help people with their chiplet designs without having to do a port first. If you think about the economics here, the further and more advanced you get in the process technology, substantially higher investment is required to do these designs and tape-outs, right, between IP and EDA tools and mass costs. There is a much higher bar now to do a chiplet or do a chip. If there is reuse that you can design into it, it is really perking people's ears up on how to do that. That is where I think the EFPGA has a lot of value. Like I said, there are several opportunities that we are tracking now, some of which are new coming out of the Intel Direct Connect conference around that, that we can be good participants in either as IP or doing the full design ourself. Okay. Thanks for that explanation. That is helpful. You talked about the $1.5 billion FPGA market in US MAG, and your unique value proposition is enabling integration. Is the catalyst that you think you will be that will enable you to make a dent into that addressable market the ability to lower the cost of verification of a product? I think you mentioned that each military use case has to be verified. Yet it sounds like you can reduce the cost of verification to a per-chip verification. Is that where you're going with that? Yes. If we step back for a moment, that $1.5 billion, obviously, is a big number. I'll give some foreshadowing if you want to go watch the video that we post later, but I give some more statistics in that presentation. Almost 75% of DOD systems use FPGAs today. It's not a lot of money in a few systems. It's a lot of money in a lot of systems. Almost all of these systems are also doing ASICs, custom ASICs or SoCs by the defense industrial base. Why are they doing ASICs? A lot of times they're doing ASICs because they can't quite get functionality out of standard products that they need for the mission. It could be that they need to have something that's of the critical nature that's designed and manufactured onshore, whereas I think almost all, if not all, FPGAs today are manufactured overseas. There is a national security aspect to this. It could just be that they need to obfuscate their IP, and they can't do that in standard products that have well-documented backdoors into the bitstream. It could also be that they're looking to lower SWaP. I mentioned that here today. I also talked about it in the presentation. SWaP is an abbreviation for size, weight, and power. Sometimes people add cost to that to make it SWaP-C. Those are all legitimate reasons why the defense industrial base is looking at doing ASICs. Again, why would you do a $150 million ASIC and then go buy a lot of FPGAs and stick it right next to that same ASIC? If you have the opportunity to integrate that into that same chip, not only are you going to get lower SWaP-C by having it all integrated together, yes, to your point, Rick, you can also reduce your qualification costs and your verification costs of multi-chips in one. Because a lot of the cost of verifying, it's the people time that you have to go through all this elaborate testing and environmental testing. If you can just do that on one chip, you're saving a heck of a lot of time. In order to get to that step of integration, you have to feel comfortable that the technology itself is far enough along that TRL curve I mentioned earlier. That's why test chips are incredibly important and impactful for the defense industrial base. They use the term burn-down risk. You do a test chip, it burns down risk of these components so that you can justify why you need to integrate that together. Those are the trends that we're seeing. Those are, I think, the drivers for why people are doing this integration of EFPGA into the ASIC. By the way, if you go look at that Intel presentation I gave, you'll see roughly the size of the ASIC market as well for the US MAG market. You can see why this makes economic sense for people to do that. I'll leave that for another time when you can go look at the YouTube video. Okay. One final question. Faraday was originally part of UMC, right? Or came from UMC? It was at Faraday. Are your other opportunities with Faraday limited to the node that the part that was announced works on? Or are you looking at maybe going smaller, like at the 12-nanometer node that UMC is working with Intel on? I would love to go smaller. Obviously, we have a big focus on selling what's available today. There is a big focus on doing what we can do and helping them with the 22-nanometer. It's public they're doing something on 12 with UMC. I think that the more comfortable that they get, they being Faraday, with this notion of embedded FPGA in an SoC, the more amenable it is to jump to that next node. The next node is probably not just for cost reasons. It's going to be for use case and applications and in market. Whereas 22-nanometer is great for low-power edge computing, 12-nanometer is probably going to be a little bit better at some other applications, more compute-intensive. We do every engagement, every partnership we enter into, we think about, yeah, there's this first step, like in the case of this 22-nanometer one, but what could it lead to? There's a huge investment by both companies to get this thing working. We want to see that it's portable to the next thing. Twelve is clearly one of those. I was pleasantly surprised to see them at the Intel Direct Connect as one of the folks doing 18A stuff. Everything that we're doing now with 22, architecturally, software-wise, business model-wise, that all leads to what we could possibly do on the Intel 18A node, which I think is a very pleasant surprise. Thanks, Brian. Thanks, Elias. Thanks, Rick. Next question is from Richard Shannon from Craig-Hallum. Please go ahead. Thanks, Brian and Elias, for taking my questions. Brian, I guess the first question is, hi. So this $1.5 billion of FPGA revenues for US MAG, I think the way that you referred to it made it sound like it was just for Intel 18A-related stuff here, but it seems like the strategic RadArm would also kind of cover the same thing. I just want to clarify. What is that exactly covering? That is an estimate of total FPGA usage by the US MAG on an annual basis, not specific to 18A. My apologies if I gave that impression. That is the annual programmable logic market today in revenue. Now, the strategic RadArm one would obviously fall under discrete FPGA, but the market that that is also trying to go into is not just limited to the FPGA market today. Because that part is actually doing something that's not available today from FPGAs. To get to some of the capability that we're designing into that, you would actually have to go to your own ASIC. From a total market perspective, it would actually be the FPGA plus the ASIC market or some percentage thereof that would be the served available market for that specific device. Okay. That makes sense. That's helpful. Okay. Now I understand a little better. Thanks for clarifying that one. Let's step over to the RadArm program here. I was typing so fast here, I may have mistyped or something here. I guess my core question here is trying to get a sense of when you think we're going to start to see storefront revenues pop up here. I get the sense that it could have been maybe talking one or two years ago, it could have been like calendar 26 or 27. Does that still fit your general timeframe, or how do we think about this? We're waiting into areas that I have asked for permission to share, and I've been denied that request. I can't give hard years as dates as much as I would like to. Let me try to give some contextual information, and you can draw your own conclusions. I think that we've been doing this development since August of 2022. When we signed that first contract, it was outlined as a four-year development. At the time, I was also allowed to say that there are two chips contemplated in this contract, a test chip and a final chip, much like you would normally do in any development. In more recent calls, I have talked about, I think, a lot more engagement with the defense industrial base, which means the end customers, and getting closer and closer in milestones to being able to get them something that they can actually start evaluating with their own designs. I'll just reiterate that like I just did from a programmatic perspective, and you can draw some conclusions from that. I am definitely spending more time now than I was a year ago directly with defense industrial base folks around this program and doing that in a way that we can make sure that we have folks lined up for when devices are available, test chips are available for them to start exercising with their own designs, which would include devices and our user tools. Okay. I look forward to the time when you actually get permission to talk about that. That will be a very interesting conversation. Me too. Believe me. I'll bet. Maybe touching quickly on Faraday, or probably more of a clarification. I was just rereading your four takeaways from this. I guess I just want to make sure. The revenues, you're not expecting any storefront revenues from Faraday directly, but you're using it to underscore the storefront business model. Is that okay? All right. That's what I thought, but I just used Faraday. It will be license and royalty because they're the ones ultimately selling a storefront device to customers. Our point in bringing them up is I think it's a very good exemplar for the storefront model where you start as services and IP, but ultimately are providing the supply chain services to the customers so that what you sell them or ship them is a finished good, and they don't have to invest in the supply chain resources and foundry and packaging relationships to get that done. All right. Maybe my last question here, and maybe it's from either of you. I think you've talked about from a yearly perspective here, getting to profits and gross margins, I think it's 60% or something like that. When you talk about solid revenue growth, I think was a term you at least you used last quarter. Any way you'd want to give us a sense of what that means quantifying? I mean, is it something similar to what you were hoping for last year, which I think was 30%? Just any way you want to help us level set a little bit. It is not 30%. It is Elias, by the way, Richard. It is not 30% for sure. Since we do not give a yearly outlook, I will tell you we are expecting a decent rebound in the second half. Let us put it this way. That gives us that confidence to be profitable and to end the year with a cash flow positive. Okay. I think that is going to be all from you guys. Thanks for taking my questions. All right. Thank you. Thanks, Richard. Our next question is from Martin Yang from Oppenheimer. Please go ahead. Hi. Thank you for taking my question. My first question is a follow-up on Faraday. In this partnership, do you expect Faraday to take on the majority of the go-to-market to sell the chip? Are you taking on any sales responsibilities? They will be the primary interface to their customer as they're talking to system companies that are wanting to do ASIC design. Because embedded FPGA is not just a USB core, as an example, and there are software tools involved in a customer using the embedded FPGA, we are definitely right behind Faraday, enabling their salesforce with different use cases and documentation and training so that it is a cohesive sell to the end customer. They will be the point person, if you will, for those customer engagements directly. Got it. Can you give us a sense of the most applicable end markets or devices that those chips will go into? Yeah. Their focus is around low-power industrial and IoT applications. If you look at what they've said publicly about this development kit, and we actually had this at our booth at the Intel conference last week. It runs an operating system. It's got a display, and it has memory on the board. The level of processing is definitely more than just a basic microcontroller. You could run some pretty good applications, including running a full operating system with user interface and GUI. I think it would be applicable for low-power edge applications. Just for further clarification, one of the use cases that we actually had discussed prior with them was what we had talked about previously when we did our Arnold chip on 22FDX, where we're able to reduce the energy consumption of edge AI applications like human presence detection. That, I think, will be one of the demos that's actually provided to customers as a use case using that platform. It was actually architected to do things like that very well. Thanks, Brian. That's it for me. Okay. Thanks, Martin. This concludes the question and answer session. I'd like to turn it forward back to Brian Faith for any closing comments. Yeah. Thank you. Thank you for joining today's call. Before we conclude, I'd like to highlight a few upcoming events where QuickLogic will be participating. May 21, the Latinberg Technology Innovation Expo in New York. If you are interested in meeting with us there, please contact Alison for details on how to register. June 23rd, we will be at the Chips and Systems Conference, formerly known as DAC, in San Francisco. On July 14th, we will be in Tennessee at NSREC. N-S-R-E-C. That is the government radiation effects focus show. We hope to see you at these events. As always, we appreciate your time, interest, and continued support, and we look forward to sharing our continued progress with you in August. Thank you and goodbye. This concludes today's teleconference. You may disconnect your lines at this time. Thank you again for your participation.