Welcome to our presentation today. Before I turn the stage over to Siva, I have to make a few very quick announcements. I need to remind everyone that today's discussion contains forward-looking statements, including regarding the company's research and development initiatives, manufacturing capabilities, and products, all of which are subject to risks and uncertainties. We assume no obligation to update these statements. Please refer to our most recent financial report on Form 10-K filed with the SEC for more information on the key risks and uncertainties. With that, I'll now turn the stage over to Dr. Siva Sivaram. Thank you, Peter. Good afternoon. Over the next 25 minutes or so, please allow me to give you my perspectives on the flash industry overall, the flash technology as it's developing, and the unique place that Western Digital plays in it. I've been in this business of non-volatile memory now for about 35 years. For those of you who are keeping track, I started working on flash when I was five years old. The technology has evolved a great deal. You would notice that periodically, on a drumbeat, Western Digital continues to develop and deliver pathbreaking products. The industry has been transformed by these products that are coming in on a regular basis. It's not just an accident that these consistent technological breakthroughs and transformational products are coming from Western Digital. There are some structural and strategic underpinnings for these. These are not just happenstances. There is a reason why we have been leaders in this field for a long time. I want to give you some background on why that is the case. Let's talk about these structural and strategic advantages that Western Digital uniquely possesses. The first of it is scale. Scale in research, scale in development, scale in product, and of course, in manufacturing. We're going to talk about that. What's unique about our technology development? What's unique about our technology, the cell technology, and the process technology? What are our unique methods of scaling, substantially different than what anyone else is doing? Our big strength in vertical integration. We'll talk about all of this more in the context of products, technology, and in how this industry itself is proceeding. As you know, flash has gone over the last 25 years from essentially starting from scratch to now being a $60+ billion industry. What happened and why is it that Western Digital has always been in the forefront of it? Before we go too far on what is it that we deliver, we do need to get a perspective on the scale of what we do. When we say NAND is a $60+ billion industry, we do manufacture in the next 18 to 24 months, the industry is going to be a zettabyte in bits delivered. In there, we have been in this business of developing products jointly with our partner, Kioxia. Kioxia, prior to that, with Toshiba Memory, and prior to that, as Toshiba. We've been working together on this joint development for the last 20+ years. Between Toshiba, Western Digital, and Toshiba Memory, and Kioxia now, we have invested over $18 billion, $18 billion in uniquely flash R&D over the last 10 years. $18 billion over the last 10 years. Between our partner and us, we are the single largest R&D investor in flash, uniquely in flash. We have successfully introduced 15 generations of flash products. You see this in context. Last year, this is data from Yole, we shipped between us about 34%. We probably produce over 35% or so of the bits in the world. Western Digital itself produce about 15%+. Even though we produce 15% of the bits, the R&D scale is of a 35% producer. Every bit that we produce gets the tender loving care plus the investment of 35% bit worth R&D. We produce about 40% of the merchant flash. I want to stand here and give an industry perspective on this. We talk about how big the flash industry is and the bits produced. A typical fab, let's say a logic fab that TSMC or Intel or Samsung or whoever does it, is about 40,000 wafers a month. A typical good size fab is 40,000 wafers per month. Our JV fab, per month, every month, over the last five years, we produced over 550,000 wafers per month. That's the scale. The Yokkaichi complex is the second-largest wafer complex in the world, and it is uniquely flash producing. This is the largest flash-producing fab complex in the world. Just to get you a perspective on the scale, if we just stack all the wafers that are produced every year and put them one above the other, it'll be about half the size of Mount Everest. Half as tall as Mount Everest, taller than many of the peaks in North America or Mount Fuji for that matter. That's the scale of this operation. Between us, we have invested $40 billion on capital in Yokkaichi. Just realize this, Western Digital is the second-largest investor in Japan outside of the U.S. government. That's the commitment that we have had in flash over the last 20 years. This gives you a perspective. Our R&D scale is much larger than anyone else because we leverage each other. When I design one die, I get another design of another die for me to ship from my partner. We do R&D together. We manufacture together. This leads us to this joint venture. How does this JV work? The most successful joint venture in the history of the semiconductors, working for the last 20 years successfully and continuing on into the future. Flash is produced by development jointly by both of us in the fabs across two manufacturing sites in Japan, in Kitakami and Yokkaichi, and Flash Ventures, our joint ventures, buys the wafers from these fabs, and they go 50/50 to Western Digital and Kioxia. The development is together. The manufacturing is together. Once the wafer comes out of the fab, we both compete openly in the marketplace. This model, which is very unique, has been very successful for the long term. Let's go from this scale, from this large manufacturing scale of having to produce half a million wafers a month every month. What is it that the technology is able to do to make that happen? Remember, we move from one node to another every 18 months, which means about 300,000 wafers per month switches over from one node to next every 18 months. That is a massive conversion from node to node that we are ahead of the world on. The logical way to do this is to make sure that these transfers are very predictable, the products are very predictable, but technology development, of course, is never predictable. You cannot schedule an invention. What do we do? As a strategy, advanced capabilities are developed ahead of need. We make sure that when we have a vast set of products, high-capacity products, low-cost products, low-power products, high-performance products, all that feeds back into what are the core process technologies needed, architectures needed, circuits under the array, multilayer stacking, wafer bonding, deep through-silicon vias, multi-wafer processing with multi-step patterning. These unit processes and architectures are developed independently, but when we need them, we integrate them into the product at the time so that we can deliver the right value to the customer at the right time. This is a big strategic thing. We don't develop technologies for the sake of developing technologies. Technologies are developed ahead so that we can integrate them and deliver it in the right form factor to the customer at the right time and value. One of the enabling features here is this idea of transfer-free manufacturing. Now, normally, most companies develop in one country, manufacture in another country. You could develop in the U.S., manufacturing in Singapore, develop in Korea, manufacture in China. We don't do that. Our development engineers with the development pilot line that is embedded in the heart of the manufacturing facility. Transfer-free. It saves about two quarters every generation in being able to develop and transfer. The fact that one crew starts, develops it, ramps it in manufacturing means there is no friction. There is no friction in that knowledge transfer. That's a unique advantage that this JV possesses. All right, we have the scale. We know how to develop and transfer. Now, what? What are we making? Why are we making what we are making? First and foremost, in the middle of all of this is this thing called a cell, a charge trap cell. A charge trap cell, which was developed about a decade and 1/2 ago with our partner, is the highest single semiconductor device ever produced and shipped by mankind. It's not a transistor, it is not a diode, it is not a capacitor, but a charge trap flash cell is the highest volume product ever shipped by the humankind. This cell at the heart of the flash device, for us to be good, has to be the best in the business. This cell, making sure that we absolutely produce the most robust cell, that's what the rest of the architecture hinges on, leverages to make this product. The charge trap cell, if you have not heard about it, the charge trap cell is the most ubiquitous device in the world, and it is by far the most sophisticated device ever built. If you did have a very good cell, what does that mean? We can then make that cell and put the rest of the architecture together with it, making sure that the right number of word lines, bit lines, charge pumps, X decoders, Y decoders, put them all together and you create a plane. If you looked at the picture of a die, usually you'll see two big planes with in-between circuits. That single plane, the ability to read and write that single plane is a good measure of how good your cell was. If your cell was good, you can write and read that plane very fast. Western Digital single plane performance is by far the best in the industry over several generations. The strength of the cell allows us to build this plane, and you can operate this plane independently. You take a cell, put this into a string, into a page that can be programmed, into a block that can be erased, in the end, you create a plane that can be independently accessed. You put additional planes next to it, you now have a device. Because this plane is so good, you know the line is, "You cannot make a silk purse with a sow's ear." When this is good, you make a good product. When this is not good, you have to do many other things to make it look better. You may have to do four planes, six planes. I got to go circuit center the area ahead of time. When this performance is good, you stay out of all of those complications, you make the best products at the right time. You don't need to do additional embellishments to make this happen. Of course, when the cell is strong, you can make multi-bit cells. You know Western Digital has always been in the forefront of multi-bit cells. We were the first to introduce MLC into the market. We were the leaders in TLC. We will be the leaders in QLC when it is the right time, when it's need to. The reason it is able to is, think of the cells. Again, go back to the cell. There is a program state and an erase state. The space between them, when it is well programmed and well erased, that space, the threshold voltage that it requires to shift from one to the other, that shows the strength of the cell. Now, unfortunately, it's not a single cell. On a wafer, approximately 300 billion of these devices that sit there, 300 billion cells in that single die. You take a distribution of all of these, when the distribution of them are wide, they end up overlapping. Making sure that distributions are tight is another unique feature of the cell. How tight is the programmed and erased state of these cells, and when is that good, we can now make an SLC to an MLC, to a TLC, to a QLC. It makes this possible. I just want to make sure you realize how important the charge trap cell is. The cell is what allows you to make sure that you can make this. Again, one more of these things that you don't realize. In a logic circuit, they'll talk about, "Oh, I just made a $10 billion microprocessor." A 10 billion cell microprocessor, if there is 10 billion cells, that die is about two inches by two inches. Very, very big. We have 200 to 300 billion of these devices on a single 100 square millimeter die. That's what makes flash scalable. I use the word scalable, and that's an extremely important factor. If you do not scale, you perish. Scale or perish has been our mantra throughout in the flash industry. You start with a flash cell, you build a device, you scale it. When you scale it, the cost per bit decreases. New markets open up. When I started in the industry, in the very early 1990s, the killer application for flash memory used to be an answering machine. That's all you could think of because the cost was so high. A telephone answering machine was considered the killer app for flash. Today, because that cost scales, new markets open up. One day, all cameras go off and we become the photography leader. Next, audio goes off, we become the leader in MP3 players. The next day, client SSDs, then enterprise, then mobile. The new markets open up because cost per bit decreases. As these markets open up, larger revenues, we've been growing at the rate of 10% compounded for the last 15 years. More money to spend on R&D, more money means better research, and you end up with cost per bit. This virtuous cycle of cost decrease, new markets, larger revenues, more R&D is what has been the cost, the fundamental underlying reason why NAND has been growing over the last 15 years. Having said that, what do we do with respect to scaling? Here we are again, very unique. Normally, you hear about scaling by Moore's law, adding more transistors in a square area. NAND achieves the Moore's law scaling even though others are diminishing in the rate of Moore's law by scaling in the third direction. You add more layers. Volumetrically, now you can scale. Scale on the X direction, Y direction, and the Z direction. The lazy man scaling is just adding more layers. The simplest thing is, aha, I need more scaling, I need more layers. You can see adding only more layers is very inefficient. If you just add more layers, it's a linear scaling. It just adds more cost. The better way is if you laterally scale and use the vertical as a lever, as a multiplier, then you can see dramatically the volume scaling helps you. This is accomplished by us getting that leadership in the areal density. There are, again, talking of numbers, a few trillion holes, these memory holes in a wafer. Few trillion memory holes in the wafer. Clearly, the customer is paying us for those bits stored on word lines that intersect these holes. The more you fit in a square area, the more shippable bits you have. People tend not to do it and just add more layers. We make sure in a unit area, maximum number of holes. This we lead in the industry. When someone tells you, "Aha, I got myself 128 layer, 168 layer, 176 layers," you have to be careful. You ask them, "Why are you 128 layers? Why can't you do with less?" This is what we have delivered with our BiCS5 generation. When the industry is saying 128 layers, we get the same scaling through 112 layers through aggressive lateral scaling. This leads to many advantages. Clearly, the capital spending is lower. Clearly, we can use prior generation equipment so that you can reuse the equipment. Clearly, the overall integration gets better. This is the reason we would consistently be 10%-15% lower in the number of layers compared to anyone else in the industry. We get much better efficient use of our fab infrastructure because of this. The last major unique advantage that Western Digital has is vertical integration. What does that mean? Western Digital does not just sell flash wafers as many do. We think of it as a system, a product system. From design to the process engineering, to manufacturing in a fab, to assembly, through test, and integrating into a product is all done by us. When every wafer moves from one generation to the next generation, as new defect modes are created, new applications are created, new ways of using it, new focus on power or performance is done, we are able to trade off the risk across all of these, and create multiple distinct products from the same die. This focus on product engineering is very unique to us. Western Digital thinks of this as a system where our own unique controllers, our own firmware platforms, our own package, our own product engineering, our own test, our own fab, our own design together makes the best integrated products that I can go say, "All right, I can make a TLC cell out of it. I can make a QLC product out of it, so that I can trade the risks between the different parts of the world. This is an important way of making sure the customer always sees a perfect product. Whatever be the risks that we trade off, whether it is in wear out mechanisms on a QLC, a performance loss in a QLC, or the higher performance on a TLC that we achieve, I can trade off one for the other and make a perfect system. The vertical integration is a unique advantage by us not just selling wafers, but by us selling systems. You can see that these structural advantages, we are unique in our scale. Our R&D gets the benefit of 35% of the bits, even though we only make 16% of the bits. We have a huge manufacturing scale. Our technology development is unique. We have a transfer-free manufacturing. We focus on the cell, and we work cell outwards. Technology is geared around the cell. We scale in a very unique, smart fashion by focusing on volumetric scaling. We believe in vertical integration. These are the structural advantages as to why we have been leaders in the past and will continue to be. Let me say this once more. Leadership is what leaders do. Leadership is what consistent leaders do. Leadership is what long-term leaders do. We have been long-term leaders in this business. That's the reason we have this consistent leadership in the past, present, and building into the future. I'll show you what we mean by this long-term leadership. As I was saying earlier, we created the industry's first multi-bit cells, two, three, four bits per cell into product, were first done by us. Industry's first 3D memory. We created and taped out the industry's first 3D memory in 2001. All of that we learned from that has now been applied everywhere. We have been creating consistently unique form factors in the industry, whether it is PCMCIA card two decades ago, CompactFlash, SD card, microSD card. All of these form factors were created as to create entirely new markets. Industry-changing interfaces. Today's mobile phone, they say, is the product of three important technologies that came together. Cellular phone technology, displays, and the memory. The memory in that came from that embedded eMMC form factor and interface that we created. The industry's first cross-point array. Other people are talking about cross-point arrays. We created and shipped them in volume by 2005. The industry's first demonstration in 3D NAND to be able to do the stacked two layers. Our 96-layer BiCS4 was two-layer memories. Of course, not to be forgotten, our partner, who develops and manufactures with this, invented both the NAND technology and the 3D NAND technology. 2D and 3D NAND were invented by our partners. Together you can see it is not just now. Over decades, we have been leaders, and we'll continue to be leaders. There comes our next generation, the BiCS6 generation, which we just announced. Again, a 162-layer 3D flash where people are talking about 176 layers and higher. We tend to minimize the number of layers. Even though we do that, number of bits per wafer increases by 70%. That's because 10% greater lateral density, 40% reduction in die size. 40% reduction in die size. Dramatic reduction in die size. The most advanced 3D cell-based performance, improved read latency, improved program performance, and of course, IO, ability to read this information fast from in and out, dramatically improved. BiCS6 is the benchmark by which all other technologies will be measured. This is the leader in the industry. I want to come back to this singular thought. Western Digital has been a leader in the industry because of the strong structural and strategic advantages and focusing on technology. It is done in a fashion that is repeatable, predictable, and stays on into the future. We will continue to deliver scaled, new flash memories to meet the vastly growing and diverse applications that our customers are demanding off of us. Western Digital is there to serve our customers. Thank you. Okay. Thank you very much, Siva. If anyone has any questions, feel free to type them in the Q&A box that's right underneath the video feed. Let me jump there real quick and start pulling up the queues. The first question here is from Aaron Rakers with Wells Fargo. Siva, why can't others do the same type of lateral memory hole scaling as WD would, assuming that the competitor is using the same exact capital equipment? It's a very good question, Aaron. The reason we do it and others is the realization over the long term as to what's important. People go get drawn to the flashy numbers of larger number of layers, which is easier to do. This requires that you consistently develop the other technologies that enable it to happen, whether it is in etch technology, whether it is in deposition technology, new materials to make sure that these are done ahead and are ready. Yes, someone else can do it, but it requires an entire infrastructure to be thinking about it. The second thing is, again, as you were saying about the scale. When we buy an etch equipment, we like to use it over multiple generations, then use the same equipment in other less demanding etches as we move up the nodes. Because we have a large install base, we are able to deploy this over time. If you are not able to, then you will have to go advance to the next generation etch tools everywhere. This is an intrinsic advantage of the scale in one place that we possess. Okay, thank you. As a follow-on to that question, today we see dual stacking, we see layer counts getting up to the 170-ish layers. If I look out a bit further into the future, how much further can we go? Can we do triple stacking? Is there a limit to the layer count? The second part of that question is what implication do these future enhancements have to the trend in cost per bit as well as overall capital expenditures? The flash industry has continued to scale over the last 15 nodes, as we talked about. We never usually have visibility past two or three nodes. I don't know how many of you remember when 2D NAND came to that cliff at 15 nanometer. We didn't have a place to go. In 3D NAND, we are still in the sweet spot. We already see a clear path for the next three nodes, whether it is we are now in volume production ramp of BiCS5, BiCS6 is being introduced, BiCS7, what we are going to do, BiCS8, what we are going to do, we already know. I do think there is plenty of runway before we run out of this current 3D NAND scaling. You know, like always, given that much time, given the amount of investment we are making in, we will have new breakthroughs scheduled so that we can get back into extending this even further. For the next decade, I would not be worried about our scaling capability and this 15%+ cost reduction annually that we are planning on in flash. Okay, the next question here is kind of an amalgamation of a number of different questions. This presentation was mainly focused on flash technology. Can you please talk about how WD differentiates itself by taking the raw NAND, which you were talking about, and bringing an actual product to market? What is WD doing that's unique or different from the competition? When he was talking about the vertical integration, there are some things to be thought of. You design a certain number of die in a portfolio, two, three die. The market needs are substantially different. For instance, an enterprise requires a very high density and relatively low power for their needs and at a certain cost level. Whereas a mobile product requires a high performance and low power. The die is the same, what do we do? We trim them to those needs. When we take a die that is coming out of the fab, you apply trims, meaning you tune the die to that particular need. When you do that, you make compromises one way or the other. Okay, is this going to be in a retail? Will you be reading it 10,000 times? No. On an enterprise, you will be reading it for 10,000 times. What do I trade what for the other? When I do that, the firmware has to know I'm doing it and be able to take advantage of it. The controller needs to have enough horsepower to be able to do it. The controllers are keeping us abreast of all of these interfaces that are coming up on the front end, whether it is USB or a UFS or a NVMe. Many interfaces are coming up. On the back end, that controller has enough oomph to talk to manage the die, to manage the flash. The firmware sits on top quarterbacking the whole thing. This ability is unique to us, that we see all of these customers at the same time. We're able to aggregate the needs, create the right distribution of risk across these different places, firmware, controller, memory, trimming, device, product engineering, et cetera. That's our unique advantage. Okay, another question just came in. Again, I think it's a little bit more future-looking. How are you leveraging your leadership in NAND and applying that to new storage class memory or SCM technology architectures, and what type of SCM architectures is WD focusing on? Let's make sure that we get our definitions right. A processor directly accesses memory, and a processor goes through an operating system to go get data from storage. Flash is a storage medium, DRAM is a memory. Why does it have to be that way? There can be something in between. That's a storage class memory. A storage class memory straddles these two. It probably may be slightly slower than a DRAM, but much cheaper, because NAND is much cheaper than DRAM. It doesn't have to be quite as fast. There are many technologies available to go do this. The more differentiated way you need to think about it is the application layers that sits on top of it need to be able to recognize these. That's where many of these storage class memories fall apart, is that, yes, you can prove a basic technology, but the software stack does not quite recognize it and works with it well. The interfaces are not coming together. Only recently, the CXL interface has opened up. Now it's openly available. Many large companies have now thrown their weight behind backing CXL. We will be developing storage class memories that work with that CXL interface. You know we are a big storage company, both on the magnetic sides and the solid-state side. We have some unique advantages. We have the best magnetics knowledge. We also have a very strong solid-state memory knowledge. At that intersection, there are solutions in storage class memory that we are exploring very carefully. Okay, here's a shorter-term question that just came in. Given you started ramping the BiCS5 in December quarter, where I believe we mentioned we're starting to ship it into client SSDs, and it's roughly a year-and-a-half cadence between nodes. Is it correct for us to start thinking that we should start seeing BiCS6-based products ramping in the second half of calendar year 2022? Or is that more a 2023 type event? Yeah. There are multiple things to think about it here. As you said, which products do you ramp on? For each product, there's a different ramp rate. A retail product or a client product will go on that 18-month cadence. An enterprise product may take longer because the qualification cycles are different. BiCS5-based products have now ramping. By end of the year, BiCS5 will be our highest volume bits that are coming out. That crossover between when the majority of the bits are on one node versus next is on a 18-month cadence. We are saying BiCS5 will reach that point in the later half of this year, and then 18 months hence, we'll do the same thing with BiCS6. Okay, here. One second. There's been a lot of discussion recently about QLC, then it was about a year-and-a-half, two years ago, where PLC first started to be talked about a little bit more broadly. What are the hurdles to bringing QLC or even PLC to market? When do you expect it to represent a bigger piece of the overall flash market? When SLC was the only game in town in the early 2000s, and then MLC, two bits per cell, came, it was a 50% increase in the number of bits for the same cost. Cost reduced by half. Huge, industry-transforming event. That patent of SanDisk, Western Digital alone, has been a milestone patent in making that happen. The system had to take care of it. When we get from MLC to TLC, three bits per cell, we get about a 33% increase in number of bits. TLC to QLC, I get only about 25% more bits for the same wafer. However, the complexity goes up dramatically. Instead of being able to sense only 8 levels, 2 to the 3 levels, now I have to sense 2 the 4 levels, 16 levels between the cells. The cell becomes slower. The cell becomes prone to having overlap between different states, so you have to decipher which level is which. Performance and endurance all suffer. You have to add additional system to make it happen. That's why the TLC to QLC has taken a little longer. Only certain markets can take that. When you go from QLC to 5 bits per cell, we can call it whatever we want later on, the growth in number of bits and reduction in cost is not very much. What you need to sacrifice to get that is going to get a lot more. It will happen. It'll happen only in specific, relatively cold applications. It's probably not in the next three years for us to think about. Okay, let me mix in a little HDD question into the mix here. The cost of an SSD per gig is always thought of having around a 10X premium to HDD cost per gig. Are there any technological inflections, QLC, PLC or other, in the next three to five years that you think could narrow the gap? That's the question. Yeah. This thought process of one replacing the other comes from our PC-based mindset. In the PC, as the cost of the flash went down, it went and displaced HDDs from laptops. In the big workloads that we are talking about in the data center, in the hyperscale data center, these are two different markets completely. The volume of bits needed that are growing, the data that is growing, today, we are introducing an 18 TB hard drive. We will be introducing 20 TB, then we show roadmaps to 30 TB and 40 TB, et cetera. However fast flash comes down in cost, will not be able to replace that level of capacity and that level of need for bits from a hyperscale data center. Cost for flash has to come down monotonically, just like we are talking about 15% a year. Hard drives are also coming down in cost over time, and hard drives are also in much larger capacities. These two in the hyperscale data center are two different applications, hot data versus cooler and cold data, where they'll have distinctly different places to occupy for the long time more. Yes, we need to reduce the cost of flash aggressively, but I don't think that is going to displace hard drive in the hyperscale data center as it did in a laptop. The next question we have here is: do you see any technology inflection that can accelerate the 15%-per-year cost improvements that WD has been talking about for quite a while? Today, the 15% cost reduction is limited by the large capital spending that you need to do to get these more layers up. As we grow up, we also want to make larger and larger capacity die. The question is: what happens to those applications that don't need the larger capacity die but they want for bandwidth reasons, smaller die? They cannot catch up with this cost reduction. The technological advances also have to keep in track with what the equipment companies are doing. The deposition, etch, lithography, wet etch, gap fill, those tools also have to come up. At today's pace, I do not see this around 15% cost reduction dramatically accelerating. Of course, there's always going to be new technologies out in the future. When we are able to get DNA storage, I promise you it'll be much, much cheaper than this. That's a few years away. Okay, the final question that we have here, and again, there's a number of different questions that are touching upon this topic. Can you please talk about the capital intensity, especially as we go from BiCS4 to BiCS5 to BiCS6? Longer term, what do you see as a trend in capital intensity? Is it going up, down, sideways? What's your view? If you looked at it in a global picture, meaning overall industry. By definition, by scaling, what we are saying is the amount of capital dollars needed to produce an extra TB has been coming down, right? That's the nature of scaling. Meaning, compared to what I used to spend to get an extra TB on a wafer in 2010 to now, it is dramatically lower. That's what 3D NAND accomplished. Even though individually, the amount of capital dollars we have spent has gone up, but the amount of bits have gone up here. We use this idea called a capital intensity. Capital intensity is the amount of capital needed to increase the production by 1%. Clearly, if there's no technology scaling, you just linearly increase more capital, more bits linearly. We want to bring that down. This does not go linearly. It's usually a tick and a tock. One generation will be low, next generation will be high, et cetera. BiCS5 for us is a very good node, where the capital intensity of the node is extraordinarily good, about the same as what it was on 2D NAND. BiCS6 will be a little bit more than that. When you average it out over multiple nodes, it tends to be about the same. It's going to remain about the same with respect to capital intensity per gigabit produced, but it is going to be much higher than what it was in our 2D NAND days. Okay. That was the last question we had. I'll turn it back to you. Peter, thank you very much. Thank you to all of you for spending the time with me this afternoon. I appreciate your audience here. Thank you. Thank you very much.